Area Efficient and High Speed 8×8 Vedic Multiplier design using Parallel Prefix Adders
Improvement of this project :
To design 8×8 Vedic Multiplier design using Brent Kung Parallel prefix adder
To design 8×8 Vedic Multiplier design using Ladner Fischer Parallel prefix adder, and compared to existing Brent Kung parallel prefix adder, and proved the performance of area, delay and power.
The design of efficient and high-performance multipliers is critical in digital signal processing and arithmetic operations. This paper describes an innovative technique to developing an 8×8 Vedic multiplier that use Ladner Fischer Parallel Prefix Adders (LF-PPA) rather than the more traditional Brent Kung Parallel Prefix Adders (BK-PPA). Ladner Fischer adders, known for their regular and modular construction, may provide benefits in terms of area efficiency. This work investigates the tradeoff associated with Ladner Fischer adder’s vs their Brent Kung equivalents in order to establish a balance between area and speed. This study includes simulation and verification techniques to ensure the accuracy and dependability of the proposed design. The iterative aspect of the design process is highlighted, with fine-tuning methods used to optimize parameters and architectures based on simulation results and synthesis using Xilinx tool input. The findings of this study add to the realm of digital arithmetic by providing insights on the feasibility and advantages of Ladner Fischer Parallel Prefix Adders in the context of an 8×8 Vedic multiplier. The proposed design is a feasible option for situations where space efficiency is a major priority without sacrificing overall performance.
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Design of High Speed 8-bit Vedic Multiplier using Brent Kung Parallel Prefix Adder
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