- Xilinx Vivado
The continuous monitoring of cardiac patients necessitates the use of a wearable system that can recognize heart problems automatically. This work describes a completely novel hardware design for the QRS complex detection based on field programmable gate arrays (FPGAs). The Pan and Tompkins algorithm forms the foundation of the proposed detection system, however the detection step makes use of a fresh, straightforward, and effective method. The novel technique to find the QRS peaks is based on the centered derivative and the intermediate value theorem. Verilog HDL has been used to implement the suggested architecture on FPGA, and Vertex-5 FPGA has been used to synthesize it. The reliability, execution time, and estimated FPGA resources of the suggested system were compared to those obtained with current QRS detection systems in order to assess the efficacy of the proposed system. The datasets from the MIT-BIH arrhythmia database have been used to verify the proposed design. Finally, compare each parameter’s area, delay, and power values.
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FPGA Heart Rate Monitoring (Pre Processing – QRS Detection Stage)
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