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Design of Approximate Restoring Divider

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Source : Verilog HDL

Proposed Abstract:

Approximate computing is an emerging paradigm in error-tolerant applications that leads to power-efficient designs without significant loss in quality. The divider in these applications have complex hardware and more latency among the computational blocks resulting in power consumption. Hence approximating the division module would lead to designs with vastly improved power efficiency. A new approximate subtractor (AxSUB) is proposed in this paper with the intent to reduce the hardware complexity while achieving accuracy within permissible limits. The proposed AxSUB and existing approximate subtractor units are used in the restoring array division (RAD) architecture to prove the efficacy of the AxSUB. This proposed architecture design with 8/4 approximate divider using Verilog HDL and synthesized using Xilinx Spartan 6 FPGA, and proved the performance of area, delay and power.

List of the following  materials will be included with the Downloaded Backup:

1. Source code ( Modelsim/ Xilinx/ Quartus/ DSCH3/ Microwind)
2. Basic Documentation (15 to 30 Pages):
2.1 Proposed Abstract
2.2 Advantages & Disadvantages
2.3 Software Related Notes
2.4 VLSI and HDL Language / Tanner Notes
2.5 References & Reference Paper for More Pages
3. Online Support ( Any Desk / Zoom / Google Meet)

 

 Software Implementation:

  • Modelsim
  • Xilinx

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Design of Approximate Restoring Divider (8/4 Exact and Approximate Architecture)

 

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Design of Approximate Restorin...

₹6,000.00

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