Description
Existing System:
FIFO buffers in NoC infrastructure are large in number and spread all over the chip. Accordingly, probability of faults is significantly higher for the buffers compared with other components of the router. Both online and offline test techniques have been proposed for test of FIFO buffers in NoC. The proposal is an offline test technique (suitable for the detection of manufacturing fault in FIFO buffers) that proposes a shared BIST controller for FIFO buffers. Online test techniques for the detection of faults in FIFO buffers of NoC routers have been proposed. However, the technique considers standard cell-based FIFO buffers, while we consider SRAM-based FIFO designs. Thus, faults considered in this brief are different from those targeted. To the best of our knowledge, no work has been reported in the literature that proposes online test of SRAM-based FIFO buffers present within routers of NoC infrastructure. Thus, we surveyed online test techniques for SRAM-based FIFOs in general. The survey revealed that SRAM based FIFOs are tested using either of the following two approaches, dedicated BIST approach as proposed by Barbagallo et al. and or distributed BIST proposed by Grecu et al.. However, both dedicated and distributed BIST approaches being offline test techniques fail to detect permanent faults, which develop over time.
Disadvantages:
- Performance in online less
- Periodic test of FIFO Memory is not Good
Proposed System:
In proposed system to increase the size of the FIFO buffer to 32bit range. The algorithmic interpretation of the transparent SOA-MATS++ test is presented in Algorithm 1. It describes the step-by-step procedure to perform the three phases of the transparent SOA-MATS++ test for each location of the FIFO memory.
For a particular FIFO memory location (present value of i), the first iteration of j (address run1) performs the invert phase, where the content of the FIFO location is inverted. The invert test phase involves reading the content of lut into a temporary variable temp and then backing it up in original. Then, the inverted content of temp is written back to lut. At this point, the content of lut is inversion of content of original.
In the next iteration of j (address run2), the restore phase is performed. The content of lut is reread into temp and compared with the content of original. The comparison should result in all 1’s pattern. However, deviation from the all 1’s pattern at any bit position indicates fault at that particular bit position. Next, the inverted content of temp is written back to lut. Thus, the content of lut, which were inverted after the first iteration get restored after the second.
The third iteration of j performs only a read operation of lut, where the content of lut is read into temp and compared with the contents of original. At this stage of the test, all 0’s pattern in the result signifies fault free location, while deviation at any bit position from all 0’s pattern means fault at that particular bit position. The last read operation ensures the detection of faults, which remained undetected during the earlier two test runs. At the end of the three test runs (iterations of j), the loop index i is incremented by one to mark the start of test for the next location.
The FIFO buffer present in each input channel of an NoC router consists of a SRAM-based FIFO memory of certain depth. During normal operation, data flits arrive through a data_in line of the buffer and are subsequently stored in different locations of the FIFO memory. On request by the neighboring router, the data flits stored are passed on to the output port through the data_out line. Fig. 1(a) shows the FIFO memory with data_in and data_out line. To perform the transparent SOA-MATS++ test on the FIFO buffer, we added a test circuit, few multiplexers and logic gates to the existing hardware, as shown in Fig. 1(a). The read and write operations on the FIFO buffer are controlled by the read enable and write enable lines, respectively. The multiplexers mu6 and mu7 select the read and write enable during the normal and test process. During normal operation when the test_ctrl is asserted low, the internal write and read enable lines, wen_int and ren_int, synchronized with the router clock, provide the write and the read enable, respectively. However, during test process, the write enable and read enable are synchronized with the test clock. As mentioned earlier, the read and write operations during test are performed at alternate edges of a test clock. The read operations are synchronized with the positive edges, while the write_clk is obtained by inverting the test clock. In test mode (test_ctrl high), the test read and write addresses are generated by test address generators implemented using gray code counters similar to the normal address generation. Muxes m4 and m5 are used to select between normal addresses and test addresses.
Advantages:
- utilize to perform online
- utilize periodic test of FIFO memory
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