## Description

**Existing System:**

In digital systems, discrete quantities of information are represented by binary codes. An n-bit binary code can represent up to 2n distinct elements of coded data. A decoder is a combinational circuit that converts binary information from n input lines to a maximum of 2n unique output lines or fewer, if the n-bit coded information has unused combinations. The circuits examined in this work are called n-to-m line decoders, and their purpose is to generate the m = 2n min terms of n input variables.

**2-4 Line Decoders **

A 2-4 line decoder generates the 4 min terms D0-3 of 2 input variables A and B. Its logic operation is summarized in Table I. Depending on the input combination; one of the 4 outputs is selected and set to 1 while the others are set to 0. An inverting 2-4 decoder generates the complementary min terms I0-3, thus the selected output is set to 0 and the rest are set to 1.

In conventional CMOS design, NAND and NOR gates are preferred to AND and OR, since they can be implemented with 4 transistors, as opposed to 6, therefore implementing logic functions with higher efficiency. A 2-4 decoder can be implemented with 20 transistors using 2 inverters and 4 NOR gates. The corresponding inverting decoder can also be implemented with 20 transistors using 2 inverters and 4 NAND gates.

**4-16 Line Decoder with 2-4 Pre decoders**

A 4-16 line decoder generates the 16 minterms D0-15 of 4 input variables A, B, C and D, and an inverting 4-16 line decoder generates the complementary minterms I0-15. A straightforward implementation of these circuits would require 16 4-input NOR and NAND gates. However, a more efficient design can be obtained using a predecoding technique, according to which blocks of n address bits can be predecoded into 1-of-2n predecoded lines that serve as inputs to the final stage decoder. With this technique, a 4-16 decoder can be implemented with 2 2-4 inverting decoders and 16 2-input NOR gates and an inverting one can be implemented with 2 2-4 decoders and 16 2-input NAND gates. In CMOS logic, these designs require 8 inverters and 24 4-input gates, yielding a total of 104 transistors each.

**Disadvantages:**

- High Transistor Count
- More Power Consumption

**Proposed System:**

In combinational logic, transmission gates have mostly been used in XOR-based circuits such as full adders and as the basic switch element in multiplexers. However, we consider their use in the implementation of AND/OR logic, as demonstrated in, which can be efficiently applied in line decoders. The 2-input TGL AND/OR gates respectively. They are full-swinging, but not restoring for all input combinations.

Regarding pass-transistor logic, there are two main circuit styles: those that use nMOS only pass-transistor circuits, like CPL and those that use both nMOS and pMOS pass transistors, like DPL and DVL. The style we consider in this work is DVL, which offers an improvement on DPL, preserving its full swing operation with reduced transistor count. The 2-input DVL AND/OR gates. Similar to the TGL gates, they are full-swinging but non-restoring. Assuming that complementary inputs are available, the TGL/DVL gates require only 3 transistors, as opposed to the 4 required in CMOS NAND/NOR gates. Decoders are high fan out circuits, where few inverters can be used by multiple gates, thus using the TGL/DVL gates can result to reduced transistor count. An important common characteristic of these gates is their asymmetric nature, ie the fact that they do not have balanced input loads. As shown in Fig. 3, we labeled the 2 gate inputs X and Y.

In TGL gates, input X controls the gate terminals of all 3 transistors, while input Y propagates to the output node through the transmission gate. In DVL gates, input X controls 2 transistor gate terminals, while input Y controls 1 gate terminal and propagates through a pass transistor to the output. We will refer to X and Y inputs as the control signal and the propagate signal of the gate, respectively. This asymmetric feature gives a designer the flexibility to perform signal arrangement, ie choosing which input is used as control and which as propagate signal in each gate. Having a complementary input as propagate signal is not a good practice, since the inverter added to the propagation path increases delay significantly. Therefore, when implementing the inhibition (A’B) or implication (A’+B) function, it is more efficient to choose the inverted variable as control signal. When implementing the AND (AB) or OR (A+B) function, either choice is equally efficient. Finally, when implementing the NAND (A’+B’) or NOR (A’B’) function, either choice results to a complementary propagate signal, perforce.

**The 14-transistor 2-4 Low-Power Topology Designing **

a 2-4 line decoder with either TGL or DVL gates would require a total of 16 transistors (12 for AND/OR gates and 4 for inverters). However, by mixing both AND gate types into the same topology and using proper signal arrangement, it is possible to eliminate one of the two inverters, therefore reducing the total transistor count to 14. Let us assume that, out of the two inputs, namely A and B, we aim to eliminate the B inverter from the circuit. The Do minterm (A’B’) is implemented with a DVL gate, where A is used as propagate signal. The D1 minterm (AB’) is implemented with a TGL gate, where B is used as propagate signal. The D2 minterm (A’B) is implemented with a DVL gate, where A is used as propagate signal. Finally, The D3 minterm (AB) is implemented with a TGL gate, where B is used as propagate signal. These particular choices completely avert the use of the complementary B signal, therefore the B inverter can be eliminated from the circuit resulting in a 14- transistor topology (9 nMOS, 5 pMOS). Following a similar procedure with OR gates, a 2-4 inverting line decoder can be implemented with 14 transistors (5 nMOS, 9 pMOS), as well: I0, I2 are implemented with TGL (using B as propagate signal) and I1, I3 are implemented with DVL (using A as propagate signal). The B inverter can once again be elided. The inverter elimination reduces transistor count, logical effort and overall switching activity of the circuits, thereby minimizing power dissipation. As far as the authors are concerned, 14 is the minimum number of transistors required to realize a full-swinging 2-4 line decoder with static (non clocked) logic. The two new topologies are named ‘2-4LP’ and ‘2-4LPI’, where ‘LP’ stands for ‘low power’ and ‘I’ for ‘inverting’. Their schematics are shown in Fig. 4(a) and Fig. 4(b), respectively.

**The 15-transistor 2-4 High-Performance Topology **

The low-power topologies presented above have a drawback regarding worst case delay, which comes from the use of complementary A as the propagate signal in the case of D0 and I3. However, realizing D0 and I3 can be implemented more efficiently by using standard CMOS gates, since there is no need for complementary signals. Specifically, D0 can be implemented with a CMOS NOR gate and I3 with a CMOS NAND gate, adding one transistor to each topology.

The new designs resulting from this modification mix 3 different types of logic into the same circuit and present a significant improvement in delay while only slightly increasing power dissipation. They are named ‘2-4HP’ (9 nMOS, 6 pMOS) and ‘2-4HPI’ (6 nMOS, 9 pMOS), where ‘HP’ stands for ‘high performance’ and ‘I’ for ‘inverting’. The reasoning behind the ‘HP’ designation is that these decoders present both low power and low delay characteristics, therefore achieving an overall good performance. The 2-4HP and 2-4HPI schematics are shown in Fig. 5(a) and Fig. 5(b), respectively, where the additional transistors are highlighted for easier distinction.

**Integration in 4-16 Line Decoders**

At a small scale, circuits based on pass transistor logic can realize logic functions with fewer transistors and improved performance compared to static CMOS. However, cascading several non-restoring circuits causes a rapid degradation in performance. A mixed-topology approach, ie alternating restoring and non-restoring levels of logic, can potentially deliver optimum results, combining the positive characterizes of both. Adopting this design methodology, and with respect to the theory presented on section II, we implemented four 4-16 decoders by using the four new 2-4 as predecoders in conjunction with CMOS NOR/NAND gates to produce the decoded outputs.

The new topologies derived from this combination are: 4-16LP ( Fig. 6(a) ), which combines two 2- 4LPI predecoders with a NOR-based post-decoder, 4-16HP ( Fig. 6(b) ), which combines two 2-4HPI predecoders with a NOR-based post-decoder, 4-16LPI ( Fig. 6(c) ), which combines two 2-4LP predecoders with a NAND-based post decoder and, finally, 4-16HPI ( Fig. 6(d) ), which combines two 2-4HP predecoders with a NAND-based post-decoder. The ‘LP’ topologies have a total of 92 transistors, while the ‘HP’ ones have 94, as opposed to the 104 transistors required by the pure CMOS implementation

** Advantages:**

- Reduces the Transistor Count
- Low power consumption