Proposed Title :

FPGA Implementation of High Speed and Highly Reliable World Fastest FFT Architecture

Improvement of this Project:

• • • To design a 16-point radix-2² fully parallel FFT as per base paper architecture and 2048-point Split Radix FFT for proposed development and finally compared all the terms of area, delay and power.

Software implementation:

• XILINX & MODELSIM

Proposed System:

This paper present a Reliable High seed communication of Fast Fourier Transformer (FFT) hardware architecture, which present break the barrier of 100 GS/s on FFT calculation. This FFT algorithm will have a highest throughput in current signal processing applications but it have barrier and pipelined complexity so it will increases multi-path delay commutate and multi path delay feedback in signal transmission and reception part. In this work will achieve the highest throughput in FFT algorithm with using Cooley Tukey approach of radix 2² 16-point parallel FFT and IFFT method, here the proposed architecture will increases pipelined  in parallel 16-point FFT architecture and reduced the barrier in high speed FFT and IFFT Communications. Finally this work will implemented in VHDL and simulated in Modelsim with Synthesize in Xilinx 14.2 and compared all the parameters in terms of area, delay and power.

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World’s Fastest FFT Architectures: Breaking the Barrier of 100 GS/s

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