Proposed Title :
FPGA Implementation of Video Coding Standard with Efficient Streaming Deblocking Filter and SAO for HEVC Decoder
Improvement of this Project:
To design a High Efficiency method of Deblocking Filter and SAO Filter for HEVC Decoder in Block size of 32×32 and 64×64.
- XILINX & MODELSIM
This paper presents a FPGA Implementation of mixed pipelined architecture and parallel processing for Deblocking filter and SAO architecture in High Efficiency Video coding (HEVC) standard. In this paper aims to developed HEVC architecture in low latency with increase throughput and reduce the number of processing cycles with using Edge filtering method of modified Horizontal and Vertical Boundaries. This proposed work will presents mixed pipeline architecture and conditions based filter decisions with multiple coding tree units on size 64×64, 32×32, 4×8, 8×4 block sizes. This proposed work is implemented on Field Programmable Gate Array (FPGA) platforms and compared with state of the literature and conclude the proposed work with 64×64 block size is suitable for all consumer High Definition applications, finally this design developed in Verilog HDL and synthesized in Xilinx Vertex FPGA XC5VFX200T-2FF1738 and compared all the terms of area, delay and power.
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Design and Implementation of Efficient Streaming Deblocking and SAO Filter for HEVC Decoder
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