Proposed Title :
FPGA Implementation of Chaos Based Bitwise Dynamical Pseudorandom Number Generator using Galois and Fibonacci series Seed Generation
Improvement of this Project:
To Design a Enhance PRNG Design with using 8-Bit, 32-Bit FIFO Buffer with 16 Depth size of Galois and Fibonacci LFSR Method of Seed Generation and proved the comparison of Area, Delay and Power.
- XILINX & MODELSIM
In this work will describe a recent research in cryptography method of Chaos based pseudorandom number generator (PRNG), these method will cooperative in the field of instrumentation and measurements in many applications such as statistical sampling, Monte Carlo simulations, evaluating the immunity to noise of digital systems and communication or procedural generations. The main contribution of this work will presents better randomness results than other PRNG with required very small amount of resources to implementation on FPGA. Here the proposed work will present a two different technique of seed generation in this Enhanced PRNG such as Galois and Fibonacci. This new technique of Galois and Fibonacci will increases better randomness in this Enhanced PRNG and it will take very less resources of area, delay and power. Here, this work will implement in VHDL and simulated in Modelsim and Synthesized in Xilinx FPGA S6LX9-2TQG144 and finally compared all the parameters in terms of area, delay and power.
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Chaos-Based Bitwise Dynamical Pseudorandom Number Generator on FPGA
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