Proposed Title :
FPGA Implementation of Error Reduction in Energy Efficient Truncation and Rounding Based Scalable Approximate Multiplier
To Modified the Arithmetic Operation of TOSAM(3,7) in Shift Unit with using Logic ‘0’ to Logic ‘1’ and reduced the Absolute Error
To Developed this proposed work with TOSAM(3,7) of 8-Bit, 16-Bit, 32-Bit and proved the compared terms of Area, Delay and Power with Error Analysis.
- XILINX & MODELSIM
In this novelty approach of Scalable approximate multiplier with using truncated rounding based technique which presents to reduced a number of partial products which based on leading one bit position. In the proposed multiplication design is performed with using arithmetic unit, truncation unit, absolute unit, shift unit for shift and add accumulation. In this operation of TOSAM (3,7) will contain more absolute error, thus this proposed methodology will modified all the arithmetic operations of shift and add unit to find a better solution and reduced the absolute error and it will proved with higher improvements of area and energy consumptions. Finally this work will designed in VHDL and simulated in Modelsim, Synthesized in Xilinx 14.2.
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TOSAM: An Energy-Efficient Truncation- and Rounding-Based Scalable Approximate Multiplier
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