POWER consumption is one of the critical design constraints in designing digital systems. Approximate computing (AC) is one of the approaches which may be used to reduce energy consumption and/or increase the speed. Since the computing result may not be correct, AC can be exploited in error-resilient applications. Examples of these applications include audio and image processing, machine learning, and data mining . More specifically, in many signal processing applications, a large portion of the energy consumption is caused by arithmetic operations (e.g., up to almost 75% of the total energy consumption of a fast Fourier transform architecture). Among these operations, multiplication, which is used repeatedly, is a high latency and energy consuming operation . This makes approximate multipliers good candidates for being employed in error-tolerant signal processing units.
Generally, a multiplication operation consists of three steps. In the first step, the partial products are generated based on the input operands. In the second step, the partial products are accumulated until only two rows remain. In the final step, the remained two rows are summed by employing a (fast) adder. One may apply the approximation to each of these steps. Approximation can be invoked in the first step to decrease the number of partial products or to decrease the complexity of their generation. Approximation may be applied in the second step of the multiplication process to decrease the latency or power consumption of the reduction levels. One of these approaches is to utilize approximate compressors. The latency and power consumption of the multiplication operation are highly affected by the architecture of the adder used in the final step of the multiplication process. Hence, one may also employ an approximate adder in the final step to improve the power consumption of the multiplier.
In this paper, we present an approximation technique for decreasing the number of partial products. In the proposed approximate algorithm, input operands are truncated to h and t bits according to the position of their leading one bit, where these truncated values are employed for the multiplication and addition operations. In addition, to reduce the error resulting from the truncation operation, we find the approximate amount of the truncated values by rounding them. These simplifications result in higher accuracy and performance compared to those of the state-of-the-art approximate multipliers. Moreover, the proposed approximate multiplier has a nearly normal error distribution with near zero mean value. The calculation core of the proposed multiplier performs multiplication and addition operations on truncated and rounded numbers and the result is shifted to the left to generate the final output. Because the arithmetic operations are performed on the truncated values, the calculation core of the proposed multiplier is small and consumes less energy compared to that of the exact multiplier. Also, the accuracy of the proposed method is mainly dependent on t and h parameter values and is not significantly affected by the width of the input operands. This provides a scalability feature for the proposed multiplier. Key contributions of this paper may be summarized as follows,
- A new scheme for the scalable approximate multiplier, which finds the position of the leading one bit and exploits both truncation and rounding operations to improve the accuracy of the multiplication operation.
- Exploration of t (truncation) and h (rounding) parameters to find a tradeoff between accuracy, delay, and energy consumption.
- Presenting hardware implementation of truncation and rounding-based scalable approximate multiplier (TOSAM) for both signed and unsigned operations.
- More energy consumption and area occupation.
- Accuracy much differ than Original output.
In this novelty approach of Scalable approximate multiplier with using truncated rounding based technique which presents to reduced a number of partial products which based on leading one bit position. In the proposed multiplication design is performed with using arithmetic unit, truncation unit, absolute unit, shift unit for shift and add accumulation. In this operation of TOSAM (3,7) will contain more absolute error, thus this proposed methodology will modified all the arithmetic operations of shift and add unit to find a better solution and reduced the absolute error and it will proved with higher improvements of area and energy consumptions. Finally this work will designed in VHDL and simulated in Modelsim, Synthesized in Xilinx 14.2.
- Less energy consumption and area occupation.
- Required accuracy is based on energy consumption which is less.