Proposed Title :
FPGA Implementation of Non-Zeroing method of 64-Bit Truncated Scalable Adder
Improvement of this Project:
To implement a Truncation Adder using in 8-Bit , 16- Bit, 32- Bit and 64-Bit
- XILINX & MODELSIM
In this Emerging technology of paradigm to dynamically reduced the consumption in applications that can naturally tolerate inaccuracies, such as multimedia, machine learning, digital signal processing and wireless communications. In this general area approximate addition has been widely explored and several approximate full adders have been proposed to approximate the least significant output bits (LSBs). In this proposed work will introduced a approximate addition with using Truncation method among many equivalent configurations in least significant bit, thus will reduced energy and increases quality outputs in terms of peak signal to noise ratio. Finally this work will designed in VHDL, synthesized in Xilinx FPGA and compared all the parameters in terms of area, delay and power and also compared with traditional truncation adders.
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Energy-Quality Scalable Adders Based on Non-zeroing Bit Truncation
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