Proposed Title :
FPGA Implementation of Non-Zeroing method of 64-Bit Truncated Scalable Adder
Energy-quality scaling is emerging as a paradigm to dynamically reduce the consumption in applications that can naturally tolerate inaccuracies, such as multimedia, machine learning, digital signal processing, and wireless communications. In this general area, approximate addition has been widely explored, and several approximate full adders have been proposed to approximate the least significant output bits (LSBs). Unfortunately, these techniques require the design of specialized standard cells, and their accuracy is statically set at design time, which is a significant limitation since it does not allow dynamic energy-quality scaling. Indeed, static assignment of the accuracy may either fail to meet higher output quality when temporarily required, or unnecessarily increase the energy in the common case. For this reason, adders should be employable in automated frameworks where the level of approximation is dynamically tuned based on the user demand. In a dynamic energy-quality tradeoff was achieved by tuning the number of truncated LSBs at run time. In particular, a bit truncation scheme was introduced to inhibit the activity of the LSBs by zeroing the corresponding input bits. However, this approach was shown to suffer from ungraceful quality degradation at larger number of truncated bits.
In this brief, a novel bit truncation approach is proposed to design dynamically energy-quality scalable adders with graceful degradation. As main idea, instead of being set to zero, the truncated input bits are set to the constant value that maximizes the output quality, while maintaining the same energy. The approach is validated in several adders in 28-nm fully depleted silicon-on-insulator (FDSOI) technology. Compared with conventional zeroing bit truncation , the proposed approach is shown to improve quality in terms of peak signal-to-noise ratio (PSNR) and mean error distance (MED) by up to 8.5 dB and 67%, respectively. More favorable energy-quality tradeoff is also observed over static approximate adders, with up to 64% energy reduction at iso-quality when scaling down the voltage. As a case study, the proposed approach was also validated in a discrete cosine transform (DCT) engine, whose PSNR is shown to be improved by up to 6 dB over existing approaches at iso-energy.
- High Area.
- More Power and Delay.
In this Emerging technology of paradigm to dynamically reduced the consumption in applications that can naturally tolerate inaccuracies, such as multimedia, machine learning, digital signal processing and wireless communications. In this general area approximate addition has been widely explored and several approximate full adders have been proposed to approximate the least significant output bits (LSBs). In this proposed work will introduced a approximate addition with using Truncation method among many equivalent configurations in least significant bit, thus will reduced energy and increases quality outputs in terms of peak signal to noise ratio. Finally this work will designed in VHDL, synthesized in Xilinx FPGA and compared all the parameters in terms of area, delay and power and also compared with traditional truncation adders.
1.1.1 Proposed Bit Truncation Scheme
Approximate n-bit addition is generally performed by splitting it into an h-bit accurate and a k-bit inaccurate part, with n = h + k. In line with prior art, ripple-carry adders (RCAs) will be considered in the following, in view of their low energy consumption. The example in Fig. 1(a) explains how two unsigned n-bit operands are truncated by zeroing their k LSBs for n = 16 and k = 8. Fig. 1 also illustrates how the approximate sum Sˆ differs from the exact sum S. The resulting output error Sˆ−S depends on k, and is equal to the sum of the errors associated with the two operands. When the operands are truncated by zeroing their k LSBs as in , the error in each operand is invariably non-positive and ranges from −(2k − 1) to 0, and hence has negative mean value. Instead, a zero-mean error would be desirable since this would allow the compensation of errors with opposite sign. Among the possible choices of bit truncation schemes, the one that maximizes quality is derived in the following, using the PSNR as common quality metric.
- Less Area.
- More Power Reduction and Delay.