Proposed Title :
CMOS Implementation of Low Power and High Security Data Information using 7T SRAM Bit cell
Improvement of this Project:
To design a 7T SRAM bit cell in 22nm CMOS technology with single bit and 8-bit level operations with compared to existing 6T SRAM bit cell in terms of area, delay and power leakage.
- TANNER EDA
In recent method of Cryptographic application based devices which have more sensitive information with more crucial part of storing and retrieving the data. Thus its affect with power analysis and side channel analysis its exploit correlation between the instantaneous current consumed power supply devices with information leakages. In this work will describe a novel security oriented 7T SRAM cell design, which incorporates a two-phased write operations and significantly reduces the correlation between the written and stored data in the memory and its power dissipation, thus its providing a power analysis resilient memory. This proposed 7T cell includes an additional transistor to the existing 6T SRAM implementation with single power gate transistor per memory. Here, this proposed work will design a 7T SRAM bit cell in 22nm CMOS technology in TANNER EDA Software with single bit and 8-bit level operations with compared to existing 6T SRAM bit cell in terms of area, delay and power leakage.
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A 7T Security Oriented SRAM Bitcell
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