A 7T Security Oriented SRAM Bitcell
The use of cryptographic devices storing sensitive information has grown considerably during the last few decades and has become a crucial part of many applications, such as smart cards, and mobile devices. Side channel analysis (SCA) is a powerful threat to these devices because it exploits the information related to the physical behavior of these devices to extract sensitive data . PA attacks are considered to be one of the most powerful types of SCA methods since they require relatively simple equipment and setups. PA attacks exploit the correlation between the instantaneous current consumed by the power supply of the device and its processed and stored data, to extract secret data or sensitive information.
Embedded memories dominate the area and power consumption of many VLSI system-on-chips (SoCs) and are key components of many cryptographic systems, such as smart cards and wireless networks employing cryptography algorithms , where they are used to store instruction code and data. Therefore, the analysis and design of secured memories is of utmost importance. Embedded memories are mostly implemented with the 6T SRAM macrocell, which provides high density, robust operation, and high performance. However, 6T SRAM arrays are traditionally designed and optimized for high density and performance, while their security properties are often overlooked, resulting in a high susceptibility to PA attacks.
Previous works have proposed modified SRAM bitcells to reduce the correlation between the dynamic power dissipation and the stored data of a conventional 6T SRAM array. Both of these solutions are based on a two-stage writeoperation. During the first stage, the internal nodes of the SRAM cell (Q and QB) are pre-charged to a constant voltage to eliminate the correlation between the previously stored data, and the write operation that follows. In the authors suggested performing the pre-charge operation by using two additional PMOS transistors beyond the original 6T SRAM in order to power-cut the supply during the additional pre-charge phase. In the authors proposed a feedback-cut SRAM cell, composed of two additional NMOS devices which are used to cut off the feedback of the SRAM cell in order to avoid shortcircuit power dissipation. While these solutions effectively reduce the correlation between the power consumption and stored data of the SRAM array, they result in significant delay and power overheads, as well as reduced static noise margins (SNMs).
In general, we assume that a side-channel attacker has access to the power supply lines of the system, and that he has knowledge of the chip architecture, including the memory organization, array peripherals and internal timing paths. In addition, it is assumed that the attacker can assign input vectors to the system, which can result in memory write operations to selected rows. Finally, it is common to assume that the overall current consumed by the memory macro peripherals and other chip components can be treated as algorithmic noise, which can be filtered out using enough current traces, especially when the memory array is operated under a separate supply voltage.
In this paper, we describe a novel security-oriented 7T SRAM cell design, which incorporates a two-phased write operation, and significantly reduces the correlation between the written and stored data in the memory and its power dissipation, thus providing a PA resilient memory. The proposed 7T cell includes an additional transistor to the original 6T SRAM implementation and a single power gate transistor per memory word, which are used to equalize the Q and QB voltages during the first phase of the write operation. Compared to other PA resistant memory solutions, the proposed cell provides 39%– 53% lower energy dissipation, 19%–38% lower write delay, and the highest read and hold SNMs compared to other PA resilient memory solutions.
A conventional 6T SRAM is shown in Fig. 1 with its signal waveforms during a write operation. To enable write access to the cell, the word line (WL) is asserted and the voltages on the bit-line pair (BL and BLB) are transferred to the internal storage nodes, Q and QB, respectively. When the written level differs from the value stored in the cell prior to the write event, the cell dissipates dynamic energy to charge the internal cell capacitances. In addition, the cell dissipates short circuit power since the access transistors (NA1 and NA2) must overcome the internal feedback of the cell (formed by transistors NPD1, PPU1, NPD2, and PPU2) to change its stored value. On the other hand, when the written value is similar to the stored data, no dynamic energy is dissipated by the cell and the total power consumption is dominated by its leakage currents.
Fig.5 depicts the current consumption during write ‘1’ and ‘0’ operations to a cell which previously stored a ‘0’. The current waveforms present a significant difference, with a peak current almost four orders of magnitude lower during the write ‘0’ (0.14 µA) operation than the write ‘1’ operation (100 µA), due to the changed state of the cell which previously stored a ‘0’.
The energy distributions obtained from a full write cycle are shown in Fig. 3, as extracted from 1000 Monte-Carlo (MC) simulations including device mismatch and process variations in 28 nm CMOS technology. As expected, the write energy dissipated during the write ‘0’ operation was over two orders of magnitude lower than the energy dissipated during a write ‘1’ operation. The mean energy dissipations for write ‘1’ and ‘0’ were 1.475 fJ and 0.016 fJ, respectively. The significant difference between the energy dissipations obtained from the different write operations to the cell indicate that the power consumption of the 6T SRAM is highly dependent on the written data to the cell, making it highly susceptible to PA attacks.
- High area occupied and more delay.
- Power analysis attack is high.
- High energy Dissipation.
In recent method of Cryptographic application based devices which have more sensitive information with more crucial part of storing and retrieving the data. Thus its affect with power analysis and side channel analysis its exploit correlation between the instantaneous current consumed power supply devices with information leakages. In this work will describe a novel security oriented 7T SRAM cell design, which incorporates a two-phased write operations and significantly reduces the correlation between the written and stored data in the memory and its power dissipation, thus its providing a power analysis resilient memory. This proposed 7T cell includes an additional transistor to the existing 6T SRAM implementation with single power gate transistor per memory. Here, this proposed work will design a 7T SRAM bit cell in 22nm CMOS technology in TANNER EDA Software with single bit and 8-bit level operations with compared to existing 6T SRAM bit cell in terms of area, delay and power leakage.
- Low Area .
- Low energy Consumption.
- Reduction in power analysis attack.
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A 7T Security Oriented SRAM Bitcell
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