DEEP Sub-micron Era in VLSI design has arrived and a cost imposed is the adoption of design methodologies that enhance the noise immunity of contemporary ICs. Noise margins are drastically exacerbated by the combination of low supply voltages and shrinking device dimensions increasing variability in several device characteristics. Process variability is attributed to the gap between manufacturing tolerances and technology scaling.The device parameters of bulk CMOS technology affected mostly are the threshold voltage, Vth, transistor interconnection length and width, and oxide thickness, which impact to a great extend both on timing and power yield. Indicative of variability effects is the fact that, moving from the 130-nm to the 45-nm technology node, standard deviation of threshold voltage almost doubled, while its nominal value inclined from almost 350 mV to 280 mV.
It is common in the literature that the device parameter variations are separated into intra-die and inter-die components for modeling purposes. Inter-die variability is due to mechanisms that induce systematic variations across a wafer, lot, or die, acting in a systematic and predictable way, and affect globally the respective device parameters . On the contrary, intra-die variations for planar bulk CMOS technologies are caused by random fluctuations and Line-Edge Roughness (LER), and/or atomic-level differences of device parameters, such as the number and placement of dopant atoms in MOSFETs . It is known that the effect of inter-die variations prevails over that of intra-die variations as the logic depth increases . Nonetheless, the contribution of the latter seems to dominate in contemporary technology nodes with low supply voltages, in which the logic depth is significantly reduced in order to maximize frequency . We employ a linear delay model in order to capture fluctuations on delays, as the linearity assumption for the delay variation modeling is common.
We mainly focus on the delay variations caused by the aforementioned mechanisms on hardware implementations of certain adder architectures. In the presence of variations, hardware architectures that exploit certain encoding schemes have been proven more efficient, under specific criteria, than conventional binary arithmetic, it is shown that multiply accumulate units based on Residue Number System (RNS) representation present better normalized delay characteristics than the binary structures with the same dynamic range. Recently, adopting CMOS BSIM 4 models, an analysis by Papachatzopoulos and Paliouras has revealed that not only does borrow-save encoding lead to hardware implementations that have substantially smaller standard deviation of maximum delay than RCAs, but they also demonstrate significant power dissipation benefits. Further prior work addresses the impact of process and environmental fluctuations on delay variations. Bernstein et al. present a variability analysis for selected 16-bit adder topologies, quantifying the normalized delay variability for each adder architecture in Static and Dynamic styles, and showing that V th variability is the primary contributor to delay variability. Alioto and Palumbo provide analytical models that allow an understanding of voltage sensitivity of Mirror and Dual-Rail Full Adders, resorting to simplified circuit models. Alioto et al. propose a framework for the estimation of max-delay variability of circuit paths that relies on the FO4 metric and on a cell-specific coefficient, which is independent of PVT conditions and technology generations. Eisele et al. demonstrate the increased normalized path delay variation of a Carry-Select Adder due to local Vth variations. Abu-Rahma and Anis develop a model for a CMOS inverter that links the variance of Vth and propagation delay, proving that they are proportional and dependent on the value of supply voltage.
Contributions: This manuscript focuses on the derivation and evaluation of two types of statistical delay-variability models for RCAs and BSAs. Specifically,
1) Formulas for the exact Probability Density Function (PDF) of the maximum output delay for the Ripple Carry Adder (RCA) and the Borrow-Save Adder (BSA) in the presence of delay variations are derived. In the following, we refer to these models as Type-I models;
2) Closed formulas are derived, given as Lemmas 1, 2, and 3, that compute the co-variances between the output delays of an adder structure, either RCA or BSA;
3) Subsequently, the derived co-variances are utilized to approximate the maximum delay distribution for each of the two architectures. The approximation relies on Clark’s expressions , and it is assumed that the delay is modeled statically, i.e., without applying any vectors at the input of the respective circuits. We refer to this model as Type-II model;
4) The agreement of the proposed models with simulation data is investigated: Furthermore using both models, it is proven statistically that BSAs outperform RCAs in the presence of delay variations. In addition, as Monte Carlo simulations of long bit-length implementations are generally prohibitive due to excessive simulation time, our models contribute to fast delay modeling for the particular adder implementations. In this context, statistical delay metrics of 4- to 256-digit BSA implementations are demonstrated and discussed.
Although less accurate than the proposed Type-I model, the Clark-based Type-II model finds applicability in Statistical Static Timing Algorithms that demand the same delay representation in all nodes of the examined circuit, referred as canonical delay models.
- High power and low density.
- High area, power and delay.
- Hardware complicity is more.
In this paper, presents a Borrow Save Encoding of two statistical delay variability in certain adder implementations. In the adder encoding method will have lot of hardware complexity and statistical delay variations, which presents in existing borrow save method of Type-I and Type-II adders with Gaussian and non-Gaussian variations sources. Most of adder encoding designed using Ripple carry adder method, this ripple carry adder will not support maximum delay compressions. Furthermore, here this paper presents a new modified method of Borrow save encoding with using Fredkin and Feynman gate to reduced the hardware complexity and statistical delay variations, here this work proved a Borrow save encoding with multiple bits such as Radix-16, Radix-32, Radix-64, Radix-128, Radix-256. Finally this work present in VHDL, Synthesized in Xilinx 14.2 and proved the parameters comparisons of area, delay and power. In this work also developed in backend design of 90-nm CMOS technology and hence proved electrical nodes, array measurements and power.
- Low power and high density.
- Low area, power and delay.
- Less hardware complicity.