Proposed Title :
FPGA implementation of Static delay variation for borrow save adder using Fredkin Feynman full adder
Improvement of this Project:
To implement a Modified Borrow Save Encoding using Fredkin and Feynman gate Full adder in Radix-16, Radix-32, Radix-64, Radix-128, Radix-256.
To implement Radix-16 Borrow Save Encoding in Backend design at 90nm CMOS Technology and taken parameter comparisons.
- Xilinx 14.2
In this paper, presents a Borrow Save Encoding of two statistical delay variability in certain adder implementations. In the adder encoding method will have lot of hardware complexity and statistical delay variations, which presents in existing borrow save method of Type-I and Type-II adders with Gaussian and non-Gaussian variations sources. Most of adder encoding designed using Ripple carry adder method, this ripple carry adder will not support maximum delay compressions. Furthermore, here this paper presents a new modified method of Borrow save encoding with using Fredkin and Feynman gate to reduced the hardware complexity and statistical delay variations, here this work proved a Borrow save encoding with multiple bits such as Radix-16, Radix-32, Radix-64, Radix-128, Radix-256. Finally this work present in VHDL, Synthesized in Xilinx 14.2 and proved the parameters comparisons of area, delay and power. In this work also developed in backend design of 90-nm CMOS technology and hence proved electrical nodes, array measurements and power.
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Static Delay Variations Modules For Ripple-Carry and Borrow Save Adders
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