Proposed Title :
FPGA Implementation of High Throughput Lossless Data Compression technique using Multi-Machine Huffman Encoding.
Improvement of this Project:
To Develop this design of High Throughput Hardware Accelerator for Lossless compression at 640 Data Bits, and a Huffman Machine will take 160 Data Bits with compared all the parameters in terms of area, delay and power.
- Xilinx 14.2
In a recent technology of digital network will transfer and receive the data with more complexity due to number of data bits and number of memory operations, thus it will take more data losses and low throughputs. Therefore this proposed work of this paper present lossless data compression with less memory architecture using Huffman compression technique. In this case here, Huffman machine will present lossless and less memory configuration and its support multi bit operations on data compression. Here, this technique will present input as 640 Data Bits and compressed output as 388 Data bits using variable length with block Huffman encoding method. The internal architecture of Huffman machine will present input as 160 Data Bits and compressed output as 45 Code words with 52 Metadata. Finally this work will present in Verilog HDL and synthesized in Vertex FPGA and get the results of area, delay and power.
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