Proposed Title :

FPGA Implementation of High Speed and Area Efficient Bidirectional Shift Register using Bidirectional Pulsed Latches

Improvement of this Project:

• To Design this Bidirectional Shift Register using Bidirectional Pulsed Latches at 256-Bit size, with compared existing of 4-shift register in terms of area, delay and power.

Software implementation:

• Modelsim
• Xilinx 14.2

Proposed System:

In a recent technology of digital application will required bidirectional shift operations to increase speed and area efficiency in all digital gadgets, therefore it will implemented many applications such as DC-DC buck converters, LDO regulators, decompresses and  digital delay locked loops.  Here, in the existing concurrent method of 256-Bit Area efficient bidirectional shift register will implemented in Back-End method of CMOS process at 65nm technology but in this case it’s not implemented these sequential bidirectional shift operations in Front-End design of FPGA Implementations, therefore this proposed work will take more area efficient and low power consumption in all FPGA applications such as Modulation and demodulation technique, Image processing, Signal processing and arithmetic applications. Finally this work present in Verilog HDL and simulated in Modelsim, synthesized in Xilinx FPGA and compared all the parameters in terms of area, delay and power.

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Area-Efficient Bidirectional Shift-Register Using Bidirectional Pulsed-Latches

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