Description

Proposed Title :

FPGA Implementation of High Speed and Area Efficient Bidirectional Shift Register using Bidirectional Pulsed Latches

Improvement of this Project:

• To Design this Bidirectional Shift Register using Bidirectional Pulsed Latches at 256-Bit size, with compared existing of 4-shift register in terms of area, delay and power.

Software implementation:

• Modelsim
• Xilinx 14.2

Existing System:

Bidirectional shift-registers are widely used in many applications, such as digital DC-DC buck converters digital low-dropout (LDO) regulators, decompresses, and digital delay locked loops (DLL) . Fig. 1 shows a conventional N-bit bidirectional shift-register consisting of N master-slave flip-flops and N 2-to-1 multiplexers. When the direction signal is ‘1’, the bidirectional shift-register shifts the data (Q) right. On the contrary, when the direction signal is ‘0’, it shifts the data left.

The conventional bidirectional shift-register uses master-slave flip-flops consisting of two latches, shown in Fig. 2(a). Its area and power consumption can be reduced by replacing the master-slave flip-flops with pulsed-latches consisting of a latch and a pulsed clock signal. But, the bidirectional shift-register using pulsed-latches cannot share a pulsed clock signal, because all pulsed-latches are enabled during clock pulse width and this causes a race condition. Therefore, the bidirectional shift-register using pulsed-latches cannot shift the data right or left. However, the shift-register using pulsed-latches in  solved this problem by using sub shift-registers and additional temporary storage latches. But, it still cannot shift the data left due to the reverse order pulsed clock signals, even if the 2-to-1 multiplexers are added such as the conventional bidirectional shift-register in Fig. 1. It also requires a long hold time to maintain the input signal.

Fig. 3 shows the schematic and operation waveforms of the proposed bidirectional pulsed-latch (BD-PL). The N-bit bidirectional shift-register can be realized by connecting the N BD-PLs in series. The differential data inputs from the left latch (DL and DL_b) are connected to the differential data outputs (Q and Qb) of the left latch. The differential data inputs from the right latch (DR and DR_b) are connected to the differential data outputs (Q and Qb) of the right latch. When the pulsed clock signal for right-shifting or left-shifting (CLK_pulse_R or CLK_pulse_L) is high, the latch data is updated to the left or right. Therefore, the BD-PL stores the left or right latch data according to CLK_pulse_R or CLK_pulse_L, respectively.

Disadvantages:

• • • High Area
    • Hold time to a Clock pulse width is more
    • More power consumptions

Proposed System:

In a recent technology of digital application will required bidirectional shift operations to increase speed and area efficiency in all digital gadgets, therefore it will implemented many applications such as DC-DC buck converters, LDO regulators, decompresses and  digital delay locked loops.  Here, in the existing concurrent method of 256-Bit Area efficient bidirectional shift register will implemented in Back-End method of CMOS process at 65nm technology but in this case it’s not implemented these sequential bidirectional shift operations in Front-End design of FPGA Implementations, therefore this proposed work will take more area efficient and low power consumption in all FPGA applications such as Modulation and demodulation technique, Image processing, Signal processing and arithmetic applications. Finally this work present in Verilog HDL and simulated in Modelsim, synthesized in Xilinx FPGA and compared all the parameters in terms of area, delay and power.

Advantages:

• • • • Low Area,
      • Its reduces the hold time to a clock pulse width
      • Less power consumption

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Area-Efficient Bidirectional Shift-Register Using Bidirectional Pulsed-Latches

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