Proposed Title :
FPGA Implementation of Multipumping Enabled with Multiported SRAM using Ternary Contenet Addressable Memory
Improvement of this Project:
- To developed TCAM based Multipumping Enabled Multiport SRAM on different case such as
- Case I = 512×28 (P=4)
- Case II = 512×32 (P=2)
- Case III = 1024×140 (P=4)
- Case IV = 2048×280 (P=4)
- Done this work in Verilog HDL, and Synthesized in Xilinx VERTEX-5 FPGA and compared all the parameters in terms of Area, delay and power.
- Xilinx 14.2
Ternary content-addressable memory (TCAM) compares an input word with its entire stored data in parallel, and outputs the matched word’s address. TCAM stores data in three states: 0, 1, and X (don’t care). Traditional TCAMs are built in application-specific integrated circuit (ASIC), and offer highspeed search operations in a deterministic time. TCAM is widely employed to design high-speed search engines and has applications in networking, artificialintelligence, data compression, radar signal tracking, pattern matching in virus-detection, gene pattern searching in bioinformatics, image processing, and to accelerate various database search primitives. The Internet-ofthings and big-data processing devices employ TCAM as a filter when storing signature patterns, and achieve a substantial reduction in energy consumption by reducing wireless data transmissions of invalid data to cloud servers. Field-programmable gate arrays (FPGAs) emulate TCAM using static random-access memory (SRAM), by addressing SRAM with TCAM contents. Each SRAM word corresponds to a specific TCAM pattern, and stores information on its existence for all possible data of the TCAM table. The increase in the number of TCAM pattern bits results in an exponential growth in memory usage. This exponential growth in memory usage has been reduced to linear growth by cascading multiple SRAM blocks in the design of TCAM on FPGA in previous work.
Contemporary FPGAs implement block-RAM (BRAM) in the silicon substrate, and offer a high speed. For example, Xilinx Virtex-6 xc6vlx760 FPGA contains 720 BRAMs of size 36 Kb, and provide operating frequencies of greater than 500 MHz. Designers utilize these high-speed SRAM blocks to design SRAM-based TCAMs on FPGA.
In existing SRAM-based solutions, the storage capacity of a BRAM for TCAM bits is limited by its higher SRAM/TCAM ratio 2 9 9 , because of its minimum depth limitation of 512 × 72 when configured in simple dual-port mode on FPGA. For example, the design methodologies proposed require a total of 56, 40, and 40 BRAMs of size 36 Kb, respectively, to implement an 18 Kb TCAM.
Excessive usage of BRAMs in the design of TCAM can result in a lack of BRAMs for other parts of the system on FPGA. Furthermore, the limited amount of BRAM resources on FPGA can compel designers to implement TCAMs in distributed RAM using SLICEM, resulting in the consumption of many slices, and a limitation on the maximum clock frequency of the design. This problem becomes more severe for the design of large storage capacity TCAMs. The efficient utilization of SRAM memory is imperative for the design of TCAMs on FPGAs.
The design of memory-efficient TCAMs requires shallow SRAM blocks on FPGAs. Multipumping-based multiported SRAM emulates the sub-blocks of a dual port SRAM block as multiple shallow SRAM blocks, by operating SRAM with a higher frequency clock, allowing access to its sub-blocks in one system cycle. Researchers have designed efficient multiported memories using BRAMs on FPGA. Existing FPGA-based TCAM design methodologies offer lower operational frequencies. This is mainly because of the complex wide signals routing between BRAMs and logic resulting from excessive usage of BRAMs and complex priority encoding units synthesized in logic slices for deeper traditional TCAMs. For example, the FPGA realizations of TCAM using BRAMs in achieve operational frequencies of 139 MHz and 133 MHz to emulate 150 Kb and 89 Kb TCAMs, respectively. The highest operational frequency achieved in the previous studies is 202 MHz for the implementation of an 18 Kb TCAM on FPGA. The demand for efficient utilization of SRAM memory in the design of TCAM and the speed provided by existing FPGA-based TCAM solutions make the use of multipumping based multiported SRAM more practical for designing TCAM memory on FPGA. Our proposed TCAM design aims to achieve efficient memory utilization with a high throughput.
The contributions of this work are as follows:
- A novel multipumping-enabled multiported SRAMbased TCAM architecture, which achieves efficient memory utilization, is proposed.
- Our proposed approach presents a scalable and modular TCAM design on FPGA.
- The proposed design is more practical for large storage capacities, owing to the reduced routing complexity achieved by the use of fewer BRAMs and the reduced AND operation complexity. The novel optimization technique of AND-accumulating SRAM words in the proposed TCAM memory units divides the overall AND operation complexity of the design.
- The proposed design is implemented on a state-of-theart FPGA. A detailed comparison of our proposed design with existing methods is performed with respect to the performance per memory. Our proposed design achieves a performance that is up to 2.85× higher per memory.
- More Complexity
- Huge Bandwidth
- Low Accuracy
- More Area and Power Consumptions
In the recent technology of digital gadgets a memory is a main priority one for storage and reterive the data, but in digital communication system the data transmission based memory will occpy more space in all gadgets, therfore this problem need to overcomes here with Ternary Content Addressable Memory(TCAM). In this existing method of TCAM design will have minimum depth limitation, which limited storage efficientcy of TCAM bits. Our propsoed work will get a solution for this limitation by mapping the existing TCAM method to Multipumping enabled with multiported SRAM based TCAM, it will configure number of sub-blocks in single TCAM with simple dual port method. Here, this paper will present a Multipumping Multiported SRAM in different limitiations such as Case I = 512×28 (P=4), Case II = 512×32 (P=2), Case III = 1024×140 (P=4), Case IV = 2048×280 (P=4). This work will implemented in Xilinx VERTEX-5 FPGA with using Verilog HDL Language and proved the better performance in terms of area, delay and power.
- Less Complexity
- Less Bandwidth
- More Accuracy
- Less Area and power Consumptions
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Efficient TCAM Design Based on Multipumping Enabled Multiported SRAM on FPGA
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