Proposed Title :
FPGA Implementation of 128-Bit Two Speed Radix-4 Serial Parallel Booth Multiplier using SQRT Carry Select Adder
Improvement of this Project:
To Design a Two Speed Radix-4 Serial Parallel Booth Multiplier using SQRT Carry select Adder at 4-bit, 8-bit, 16-bit, 32-bit, 64-bit and 128-bit. Finally compared this all the parameters in terms of area, delay and power.
- Xilinx 14.2
In a recent all digital signal processing and machine learning applications will have priority one is multiplication its most important to dictate the area, delay, power and improve overall performance with parallel implementations. In this case these number of multiplication will have number of arithmetic additions and subtractions it will take more logic sizes with critical paths and more power consumptions. Due to resolve this problem here, this proposed work will present optimization of radix-4 multiplication circuits has been extensive using modified booth algorithm with SQRT carry select adder to improve overall performance and reduce logic sizes with critical paths compared to Wallace tree and DADDA Multiplier. Finally this work will present in Verilog HDL, and synthesize in Xilinx FPGA and proved comparisons terms of area, delay and power.
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A Two-Speed, Radix-4, Serial–Parallel Multiplier (Booth Multiplier )
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