CMOS First-Order All-Pass Filter With 2-Hz Pole Frequency
ALL-PASS FILTERS (APFs) have wide usage in signal processing. They can be used in group delay (GD)/ phase equalizers, frequency-selective filters with a high-quality factor, etc. It is also an important block of quadrature and multiphase oscillators. As it can provide time delay, it can be used in differential modulation and beamforming schemes as well. A first-order APF introduces a −90◦ phase shift at a frequency f0 (called pole frequency), whose value is inversely proportional to an RC time constant. Most reported integrated APFs have a pole frequency f0 in the kilohertz–gigahertz range. The goal of this paper is to implement a fully integrated APF with very low f0 in the range of Hz. This low f0 frequency is necessary for some applications like in rotating disk viscometer , sensor-based medical devices that perform parallel processing of the sensed biological signal which has frequencies below 100 Hz. Viscometer can detect blood viscosity, which helps to determine many diseases such as diabetes mellitus, malaria hypertension, and ischemic stroke. The rotating disk viscometer needs uniformly rotating magnetic field which can be generated by two stable quadrature sinusoidal waveforms in the range of 0.5–50 Hz. APFs can generate quadrature sinusoidal waveforms. APFs can also be used to build linear phase equalizers which act as a delay line. This is necessary to provide synchronization between different parallel processing blocks of real-time signal processing medical devices such as electroencephalography systems. The frequency f0 in the proposed APF is given by an expression of the form f0 = 1/(2π RC). Hence, to obtain a low-frequency f0 in the Hz range, very large capacitor C and resistor R values are required. However, implementation of large capacitor and resistor values in standard CMOS technology with available conventional resistors and capacitors would take extremely large silicon area. In this paper, large valued resistors are implemented using the leakage resistance of the reverse biased source-bulk and drain-bulk p-n junction within a pMOS transistor operating in the cutoff region. A large valued resistor can be emulated using switched-capacitor topology as well, where a two nonoverlapping clock needs to be generated. A linear differential Miller amplifier is used to emulate large capacitors (∼100 pF) using Miller effect from a moderately valued physical capacitor C (∼pF). These large valued resistances and capacitors can provide a very low cutoff frequency. By varying the gain of the Miller amplifier, variable Miller capacitors can be realized, which in turn provide adjustable pole frequencies which can be used to tune f0 to compensate for manufacturing and temperature variations.
- Taken more Silicon Area size and time delay
- More power Consumption
- Taken more size in conventional resistors and capacitors
Due to its versatility, the linearized operational transconductance amplifier (OTA) is the basic building block of many linear and nonlinear analog circuits, such as continuous-time oscillator and filters. The proposed circuit is based on a linear OTA architecture.
The differential input stage uses resistive degeneration to transform the differential input voltage Vd = V + in − V − in linearly into a signal current with value i = Vd /ROTA. The complementary signal currents, in M1, M1P (i and −i) are mirrored to the output branches of the OTA through two paths that add their currents in cascoded transistors M3C, M3CP. In one of the paths (M3, M3P), the current i is replicated with unity gain. In the second path (through M3DL, M3DLP), the current is mirrored with a current gain −2 and filtered by first-order RC low-pass filters connected between nodes V + x , V − x , and nodes VB and VA at the gates of M3DL and M3DLP. Cross-connections are used to achieve inversion of the low-pass filtered currents (iLPF) in M3DL and M3DLP. The LPFs have a 3-dB frequency ωo = 1/(RlargeCM ) where CM is a Miller capacitance and Rlarge are very high valued resistors. As the low-pass filtered current in M3DL (M3DLP) is twice the current of M3(M3P) and inverted as well, the resultant current is is given by
is(ω) = 2iLPF(ω) − i(ω)
= (Vd (ω)/ROTA) 2 (1 + jω/ω0) – 1
= (Vd (ω)/ROTA) (1 − jω/ω0) (1 + jω/ω0) …… (1)
The output voltage of the filter is given by
VOut(ω) = (ZL||ROut)iout(ω)
= 2(ZL||ROut)is(ω) ….(2)
where ROut is the output impedance of the OTA, buiding block of the APF. The load impedance of the filter is given by
ZL = (RL ||XC)
= RL /(1 + jωCL RL )……. (3)
Hence, using (1)–(3) the transfer function is given by
H(jω) = 2 ROTA (RL ||ROut) 1 + jω ωPout (1 − jω/ω0) (1 + jω/ω0) …….. (4)
ROut can be expressed by ROut = gmr 2 o /2 where gm is trans conductance gain and ro is output resistance of the output transistors. Assuming ROut RL , the output pole of the filter is given by ωpOut ≈ 1/RLCL . Now, if ω0 is extremely small compared to the output pole ωpOut(ω0 <<< ωpOut) for frequencies ω <<< ωpOut (4) can be approximated by
H(jω) = 2(RL/ROTA) (1 − jω/ω0) (1 + jω/ω0) ……(5)
Hence, (5) corresponds to the transfer function of a first-order APF with gain Kfil ≈ 2RL/ROTA and pole frequency f0 = 1/(2π RlargeCM ). For ROTA = 2RL, the APF has unity gain. The two important characteristics of the first-order filters are its phase and GD. The phase response of the filter obtained from (5) is given by
= −2 tan−1(ω/ω0)……. (6)
The GD of the APF is given by (7). GD variations are a measure of the phase nonlinearity. If there is a linear phase variation with frequency, GD must be constant. A first-order APF does not provide linear phase shift. However, by increasing the order of filter linear phase shift can be approximated
GD = −dφ dω = 2 1 + (ω/ω0)2 1 ω0 …… (7)
The bandwidth (BWAPF) of the APF is determined by the high-frequency dominant pole fpOut located at the output node VOut. The fpOut can be expressed by (8) when RL ROut and CL is the load capacitance
fPOut = 1 2π RLCL …… (8)
The pole frequency f0 with value in the order of Hz can be achieved by utilization of the leakage resistance of two diode-connected pMOS transistors operating in cutoff mode. Fig. 2 shows the implementation of these large valued resistances. From Fig. 2, it can be observed that two p-n junctions are formed. One is between the source and the n-well. The second one is between n-well and drains region. As the n-well is connected to VDD, the p-n junctions are reverse biased. The leakage resistance of these reversed biased p-n junctions provides a very large resistance when the diode-connected pMOS is in cutoff region. These two large valued resistors are connected to the gate of the M3DL and M3DLP in Fig. 1 and provide well-controlled dc gate bias voltage. These two transistors are called quasi-floating gate transistors. This technique has been used to implement extremely large resistors (Rlarge ∼ 10–100 G) for many applications. Miller multiplication effect is also used in this paper to emulate large capacitors from relatively low valued physical capacitors depending on the gain of the amplifier (in the example presented here CM ≈ 310 pF).
- Taken less Silicon Area size and time delay
- Less power Consumption
- Taken less size in conventional resistors and capacitors
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CMOS First-Order All-Pass Filter With 2-Hz Pole Frequency
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