## Description

**Existing System:**

The bandwidth (BW) of the CMOS conventional voltage follower (CNV-VF), shown in Fig. 1, is given approximately by BWCNV = gm1/2πCL , where gm1 is the transconductance of M1 and CL is the load capacitance. The negative slew rate (SR−) of the circuit is limited by the bias current IB to a value SR− = IB/CL , while the positive slew rate (SR+) can have a relatively large value, since the maximum positive output current is not limited by IB. In practice, a symmetrical slew rate (SR) is desirable, since the lowest of the positive and negative SRs limits the large signal speed. This means that in practice, the SR corresponds to min {SR+, SR−}. Both the SR and the BW can be increased at the expense of increasing IB and consequently the static power dissipation. In the modern submicrometer CMOS technology, low power consumption is a key requirement for increasing the battery life of portable systems. Class AB VFs (CNVAB-VFs) can boost the maximum negative output current (and consequently SR−) without increasing the static power dissipation essentially.

Till date, many different CNV-ABVFs have been reported that have improved the SR without improving the BW. Often, the desired class AB operation is achieved at the expense of increasing the supply voltage, the power dissipation, circuit complexity, and the silicon area. A comprehensive survey of buffers/VFs can be found in [4]. For high-speed applications, both the SR and the BW are equally important (see discussion in Section V). In this paper, we propose a simple and power efficient CNV-ABVF. The proposed CNV-AB-VF dissipates the same quiescent power as a CNV-VF but has much higher SR and BW. Three figures of merits can be used to characterize and compare the performance of VFs. First, the current enhancement figure of merit, FOMCE = IoutMAX/IQtotal, where IoutMAX is the maximum output current and IQtotal is the total quiescent current. This is related to the SR improvement and the large signal performance of the circuit. Second, the BW figure of merit , FOMBW = BW(MHz)CL (pF)/P Q (μW), where P Q is the total quiescent power dissipation of the circuit. Since FOMCE determines the speed limitation for large signals and FOMBW limits the speed of small signals, a third global speed figure of merit can also be defined that corresponds to the geometric mean of the previous two figures of merit FOMGLB = (FOMCEFOMBW) 1/2.

**Disadvantages:**

- High power and low density.
- High area, power.
- Hardware complicity is more.

**Proposed System:**

In this recent signal processing application of digital products will have a high priority in bandwidth allocations, in this method of signal transmission and reception will cause additional complication to demodulated original data, it will affected bandwidth and slew-rate due to more signal traffic in today digital world. In this paper describe a conventional voltage follower (CNV-VF) with enhanced bandwidth and slew rate with static power dissipations. In this proposed method of CNV-AB-VF can boost the maximum output current without increasing the static power dissipations and enhanced the slew rate using some more additional transistors, and here this proposed work will compared CNV-AB-VF method to existing method of CMOS FVF. Finally this work developed in TANNER EDA, and compared all the parameters in terms of area, delay and power.

In a Proposed Voltage Follower method of class AB flipped VF (FVF) reported it shown in Fig.5(a) with an additional transistor M1AB, which operates as a CNV-VF and can improve SR+. However, its output swing is limited by the gate–source voltage of M2. The input/output peak-to-peak swing is given by Vinpp = VT –VDSsat, where VT is the threshold voltage of the transistor. This swing is very small and independent of the supply voltage. This is a very serious limitation, since in the modern technology, lower values of threshold voltage (VT ∼ 0.4 V) are used. Maximum peak output signals of the circuit in with a low distortion are on the order of only 0.15 V. Fig. 5(b) shows a CNVAB-VF (CNV-AB-VF) reported in that has a resistor RL inserted between the drain of M1 and VDD. M1 and M2 have equal quiescent currents IB. It can be considered as a dynamic FVF without the swing limitations of the circuit in Fig. 5(a), since the dc operating points at node Vx is independent of the dc operating point at node VY and they are connected in the presence of ac signals. The circuit in Fig. 5(b) operates as follows: transient variations in Vin generate variations in Vx which are 180◦ out of phase with Vin.

These variations are transferred from node VX to node VY using a capacitor CBAT that acts as a floating battery for fast changes in VX . Furthermore, Rlarge and CBAT form a high-pass circuit for signals passing from VX to VY . This changes the current of M2 as a function of the variations in Vin. Negative (positive) values of Vin leads to positive (negative) values in VX and VY , which increase (decrease) the dynamic drain current of M2. This leads to maximum negative output currents that can be essentially larger than IB and therefore much higher negative SR than the CNV-VF. An additional advantage of the SR enhancement circuit (RL , Rlarge, and CBAT) is that the local negative feedback through CBAT in the presence of ac signal decreases the output impedance of the follower by the gain 1 + gm2RL of the negative feedback loop. This also helps to enhance the BW of the follower, as explained in Section III. In the circuit shown in Fig. 2(b), both the BW and the maximum negative output current (and SR−) increase with RL . However, the increase of RL leads to a decrease in the maximum positive output current (and in the SR+), since it is in series with the drain of M1. This does not allow optimizing SR+, SR−, and BW simultaneously. The proposed VF is shown in Fig. 5(c). It overcomes the limitations of the FVF shown in Fig. 5(a) and of the CNV-AB-VF shown in Fig. 5(b). It is derived by merging the conventional follower in Fig. 1 with the circuit in Fig. 5(b). This is done by adding a transistor M1AB connected as a CNV-VF. M1AB can provide a large positive output current which is independent of the value of RL . To maintain equal quiescent power dissipation as the CNV-AB-VF and the CNV-VF, the current mirror ratio W2P/WB of the proposed VF is 1:1 where W2P and WB are the widths of M2P and MB. From this point, the proposed circuit in Fig. 5(c) will be denoted as “PRP-AB-VF.” As it is shown in Section III, the PRP-AB-VF can deliver simultaneously nearly symmetric and large maximum positive and negative output currents and exhibits moderate-to-high BW enhancement with little area overhead and with the same static power dissipation, as the CNV-VF in Fig. 1. In this paper, the PRP-AB-VF is intended to be used as a buffer for amplifiers. In order to perform a comparison, the small signal analysis of the circuit in [10, Fig. 5(b)] is also included here, since [10] does not include the analysis of the circuit’s BW. The focus of this paper is to demonstrate that the proposed circuit has significantly enhanced BW with respect to the circuit shown in Fig. 5(b) and simultaneously high symmetrical SR. The circuit in Fig. 5(a) is not included in the comparison due to the swing limitations.

** Advantages:**

- Low power and high density.
- Low area, power
- Less hardware complicity.