High accuracy TDCs are key building blocks for many science and engineering applications such as laser range finder, jitter measurement, time-of-flight (TOF) experiment, PET (positron emission tomography) scanner … and so on. The major requirements for main stream applications include wide measurement range, high resolution, low cost and low process, voltage and temperature (PVT) sensitivity. To achieve resolutions better than 10 ps, most TDCs are implemented in application-specific integrated circuits (ASIC) which tends to be cost ineffective, especially for small-scale productions. On the contrary, implementation with FPGA platforms is capable to provide low cost solution due to fast prototyping. Furthermore, FPGA TDC can embed the required digital auxiliary circuits to realize more functions for creating much complete and powerful applications.
In the past, TDC with resolution less than 1ns could be realized with both power- and area-consuming ECL logic unsuitable for integrated chips or portable systems. In order to achieve wide measurement range and high resolution, many techniques have been developed, such as Vernier principle, time-to-amplitude conversion, time stretching, and time interpolation. Theoretically, a counter incrementing every clock cycle is the simplest TDC implementation. With the help of a time-consuming look-up table (LUT), 3-ps incremental resolution is achieved. To obtain wide measurement range, multi-stage interpolation can be applied. The conceptual timing diagram of two-stage time interpolation technique based on the classic Nutt method is shown in Fig. 1 where Tin (the input signal) is segmented into T12, T1 and T2. T1 and T2 with durations less than one clock period TCLK are converted by fine TDCs or interpolators with resolutions much smaller than TCLK while T12 is synchronous with the reference clock CLK and can be simply digitized by a coarse counter.
Many structures are proposed to enhance the interpolator accuracy. Among them, pulse stretcher (dual-slope conversion), tapped delay line, pulse shrinking and Vernier delay line (differential delay line) are the most commonly used to achieve sub-gate delay resolution. Even after long term evolution, to accomplish an effective resolution better than 10 ps for TDCs is still a challenge for experienced designers. More advanced techniques are required. Time amplification is used to realize a 9-bit, 1.25-ps LSB width and less-than-one-LSB output standard deviation TDC. The DNL and INL are measured as 0.8 LSB and 3 LSB with limited dynamic range. Cyclic time-domain successive approximation is created to get 327 μs dynamic range and 1.2 ps resolution. By using an external integral nonlinearity look-up table (INL-LUT) for the interpolators, 3.2-ps RMS single-shot precision is achieved. Vernier ring is invented to implement a TDC with 8 ps bin size and an output standard deviation < 1 LSB. A gated Vernier ring structure is composed to further improve the TDC performance to realize an equivalent resolution of 3.2 ps with an oversampling ratio of 16. An 8-bit Cyclic TDC is proposed to achieve ±0.7 LSB DNL, -3~+1 LSB INL and 1.25 ps LSB width. Time-domain ΔΣ modulation for noiseshaping is adopted to enhance dynamic accuracy for applications with periodic TDC input, to achieve an effective resolution around 6 ps.
Although it is not impossible, only very few analog applications can be realized in pure standard cell-based design with performance comparable to full-custom one’s. Even fewer of them can be successfully implemented with FPGA chips due to the lack of aspect ratio tuning and bias adjustment. The most common way of building cost-effective FPGA TDC is to utilize tapped or Vernier delay line. A CMOS FPGA TDC based on Vernier delay line is proposed to realize 200 ps average resolution which is further improved to 100 ps LSB width. The single-shot resolution is reduced to 75 ps for TDC with a two-step cascading delay line. By using two controllable ring oscillators with very small difference in frequencies, 40 ps resolution is verified based on Vernier principle and self-calibration. By using a series of calibration strategies, 25 ps RMS resolution is obtained along with 50 ps bin size for carry-chain-based TDC. However, carry chain suffers from serious uneven tap delay. The interblock delay is much larger than the intra-block one at the block boundaries. The RMS resolutions can be enhanced to be 30.9 ps, 18.5 ps and 14.2 ps correspondingly with bin-by-bin calibration or chip-specific DNL compensation. A novel wave union launcher is designed to make multiple measurements with a single delay chain structure to effectively sub-divide the ultra-wide bins in each raw measurement. With the average of 16 measurements, the RMS resolution is improved from 40 ps to 10 ps. More efforts are made since after to refine the FPGA TDC resolution by averaging and calibration to achieve an RMS resolution around 10 ps. It makes the FPGA TDCs closer than ever to the state-of-the-art full-custom ones in performance.
A brand new linearization technology based on delay wrapping and averaging is presented in this paper to explore the uttermost capability of FPGA TDC for further narrowing down the performance gap between FPGA and full-custom TDCs. An excellent performance of 2.5 ps bin size and 5.81 ps RMS resolution is verified by experiments without the need of any cost- and time-consuming bin-by-bin calibration.
- TDC achieves resolution of 2.5ps.
- Power and area consuming is high.
Time to Digital Converter provides the digital representation of time when it occurs. The major requirements for main stream applications include wide measurement range, high resolution, low cost and low process, voltage and temperature (PVT) sensitivity. To achieve resolutions better than 10 ps, most TDCs are implemented in application-specific integrated circuits (ASIC), which is ineffective. Therefore, This paper proposes the new concept of Time-to-digital Converter(TDC) FPGA with high resolution of 2ps(picoseconds) bin size. This concept increases the performance of TDC in order to achieve a high resolution. In this concept the signals are sampled with n number of times and timing reference is generated by feeding original clock into tapped delay line. According to periodicity, the delays among those timing references are wrapped into a single reference period and the effective TDC resolution can be made much smaller than the clock period to compete even with the state-of the art full-custom TDCs in performance. Finally, this concept of High resolution of TDC is implemented in the VERILOG and Synthesized using XILINX and shown the comparison in terms of delay, power and area reports.
As the conceptual timing diagram shown in above figure, if the clock frequency is designed to be high enough, the inaccuracy at both ends of the input Tin caused by the fractional periods T1 and T2 can be neglected to fulfill high accuracy. However, the TDC counter is required to operate at THz range to accomplish ps-level accuracy which is totally impractical. One possible solution is to feed the reference clock CLK into a tapped delay line to generate multiple delayed clocks for time quantization to achieve an effective resolution less than the reference clock period TCLK. Analogy to TDC based on tapped delay line, the above figure illustrate the TDC schematic and timing diagram with Tin quantized by multiple delayed clocks. Since all counter outputs are summed together to get the final result, the circuit is equivalent to a simple counter-based TDC with a reference clock period of τ (τclk) instead of TCLK as depicted in Figure. The effective resolution becomes the cell delay or the phase shift among the delayed reference clocks. As a consequence, the FPGA logic gate delay limits the achievable TDC resolution. Fortunately, if a specific clock delay or phase shift is larger than TCLK, it will be wrapped back into the reference clock period due to the periodicity of the clocks as revealed in Fig . where one period of CLK (also named as C0) is chosen to be the reference clock period for easy comprehension.
However, it is neither necessary nor easy to make τ larger than TCLK for advanced FPGAs with intrinsic gate delay of merely tens of picoseconds. Only if the delay line is long enough, phase wrapping still occurs to fully cover the reference period by delayed clocks, as shown in Fig. To generate extremely fine TDC resolution, the effective resolution Δτ can be designed to be much smaller than both τ and TCLK. The difficulty for practical implementation is that it is not only impossible to keep the same phase shift τ among delayed clocks but also even harder to achieve homogeneous Δτ after phase wrapping due to device mismatch and Automatic Place and Route (APR) parasitics. Special cares need to be taken during realization.
When necessary, multiple TDC cores can be constructed on the same FPGA chip to average their outputs for both linearity and RMS resolution enhancement.
During circuit implementation, the pulse-shrinking / stretching mechanism caused by the aspect ratio mismatch among adjacent devices will limit the realizable length of the clock delay line. Since the pulse width of high frequency clock is rather small, it is much vulnerable to pulse-shrinking / stretching mechanism. The input Tin instead of the reference clock CLK can be fed into the delay line to create equivalent time quantization shown in Figure. The block diagram of the proposed TDC is depicted in Figure. The delayed input signals are synchronized to the reference clock for meta-stability reduction and then fed into corresponding counters for quantization. As seen in (2), the longer delay line the better TDC resolution. Table I reveals the measurement results for Altera Stratix IV according to 128, 256 and 512 delay line length. Even though both nominal and RMS resolutions are improved for longer delay line, the linearity is worsened on the contrary.
To enhance linearity, we try to realize multiple TDC cores and take their average as the final conversion output as illustrated in Figure. The TDC performance versus the number of implemented cores is summarized. Under the same nominal resolution of 2.5 ps, the RMS resolution and INL are successfully improved from 6.515 LSB and 13.1 LSB to be 2.322 LSB and 6.53 LSB. The corresponding DNL and INL are shown in Fig. The performance is even better than some of the outstanding full-custom TDCs. The innovation and superiority of the proposed TDC is thus proved.
- Achieves high resolution of 2ps bin size.
- Performance of TDC is high.