Proposed Title :

FPGA Implementation of 2ps-Bin Size with 512 length of High Resolution FPGA TDC Converter

Improvement of this project :

• To develop a VERILOG code for High performance of FPGA time-to-digital Converter(TDC).

• The TDC is implemented with effective resolution of 2 ps(picoseconds) with the length of 512.

Software implementation:

• Modelsim
• Xilinx

Proposed System:

Time to Digital Converter provides the digital representation of time when it occurs.  The major requirements for main stream applications include wide measurement range, high resolution, low cost and low process, voltage and temperature (PVT) sensitivity. To achieve resolutions better than 10 ps, most TDCs are implemented in application-specific integrated circuits (ASIC),  which is ineffective.  Therefore, This paper proposes the new concept of Time-to-digital Converter(TDC) FPGA with high resolution of 2ps(picoseconds) bin size.  This concept  increases the performance of TDC in order to achieve a high resolution.  In this concept the signals are sampled with n number of times and timing reference is generated by feeding original clock into tapped delay line.  According to periodicity, the delays among those timing references are wrapped into a single reference period and the effective TDC resolution can be made much smaller than the clock period to compete even with the state-of the art full-custom TDCs in performance.  Finally, this concept of High resolution of TDC is implemented in the VERILOG and Synthesized using XILINX and shown the comparison in terms of delay, power and area reports.

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A High Resolution FPGA TDC Converter with 2.5 ps Bin Size and -3.79~6.53 LSB Integral Non linearity