Due to the rapid development of technology, the scenario of digital industry has changed in the past few years. Intel co founder Gordon Moore in 1960 predicted that the number of transistors on a single chip will double in every eighteen months. According to his prediction, the conventional CMOS based devices advanced from micron to sub micron, sub micron to deep sub micron and to nanometer regime over last five decades. But the scaling of CMOS devices at nano scale affects the performance of several factors like heat dissipation and leakage currents. The heat generated can no longer dissipate and results in damage of the chip as more and more devices are packed into the same area. So many novel technologies and materials have been extensively researched and developed at nano scale to replace conventional transistor based VLSI technology. Among several other alternatives, Quantum Dot Cellular Automata (QCA) is a revolutionary promising transistor less quantum paradigm that performs computation and routing information at nano domain. The unique feature of QCA is that logic states are represented by a cell. A cell is a nano scale device capable of transferring data by two state electron configurations. The advantages of QCA over conventional CMOS technology include lesser delay, high density circuits and low power consumption which permits us to perform quantum computing in near future.
REVIEW OF QCA
The basic logic unit of Quantum Dot Cellular Automata is based on QCA cells which contain four quantum dots arranged in a square pattern. Each cell contains two mobile electrons which can tunnel quantum mechanically between dots. Due to the mutual columbic repulsion, the electrons in quantum dots confined in the potential well will always try to occupy the two possible diametrically opposite positions of a square shaped cell. Unlike conventional transistor logic, QCA connects the state of one cell to the state of its immediate cells by columbic interaction. The state of a cell is called its polarization defined by P. Therefore, two distinct cell states exist. Figure-1 shows two possible minimum energy states of a quantum dot cell. It is assumed that logic ‘0’ as cell polarization P =-1 and logic ‘1’as cell polarization P=+1.
- Requires large area.
- QCA technique has some disadvantages such as ultra-thin gate oxides, short channel effects, leakage currents & excessive power dissipation
- Complex hardware implementation.
Quantum Dot Cellular Automata (QCA) is a transistor less quantum paradigm that represents the binary information which is based on spatial distribution of electron charge computation and routing information at nano domain. This paper proposes the new design concept of different flip flops which includes SR, D, T and JK in GDI(Gate Diffusion Input) logic. The existing system uses the concept of QCA technology to implement these flip flops, but it consumes more area, power and it also faces the complexity in hardware implementation. This technology has a surface defects, which can affect the combination of electrons and holes in the circuit. Therefore this paper proposes the concept of GDI technique in order to reduces the area and design complexity. Thus, the proposed system of GDI Technique flip flops reduces the area, power and hardware complexity when compared to existing system of flip flop design using QCA logic. The proposed system has been implemented in 45nm CMOS technology at 1.8V supply voltage and shown the comparison in terms of area, power and delay.
With rapid development of portable digital applications, the demand for increasing speed, compact implementation and low power dissipation triggers numerous research efforts. The wish to improve the performance of logic circuits, once based on traditional CMOS technology, results in developing of many logic design techniques during the last two decades. One form of logic that is popular in low-power digital circuits is pass-transistor logic (PTL).
Formal methods for deriving pass-transistor logic have been presented for nMOS. They are based on the model, where a set of control signals is applied to the gates of n-transistors. Another set of data signals are applied to the sources of the n-transistors. Many PTL circuit implementations have been proposed in the literature.
Some of the main advantages of PTL over standard CMOS design are: (1) High speed – due to the small node capacitances, (2) Low power dissipation – as a result of the reduced number of transistors, (3) Lower interconnection effects – due to a small area.
However, most of the PTL implementations have two basic problems. First, the threshold drop across the single-channel pass transistors results in reduced current drive and hence slower operation at reduced supply voltages; this is particularly important for low power design since it is desirable to operate at the lowest possible voltage level. Second, since the “high” input voltage level at the regencrative inverters is not Vdd, the PMOS dcvicc in the inverter is not fully tumcd off, and hence dircct-path static power dissipation could be significant. An additional problem of existing PTL is top-down logic dcsign complexity, which prevents from the pass-transistors capturing a major role in real logic LSl’s. One of the main reasons for this is that no simple and universal cell library is available for PTL based design.
GDI (Gate Diffusion Input technique) – a new low powcr dcsign technique, which allows solving most of the problems mcntioncd above was presented. GDI approach allows implcmcntation of a wide range of complex logic functions using only two tran’sistors. This method is suitable for design of fast, low power circuits, using reduced number of transistors (as compared to CMOS and existing PTL techniques), while improving powcr characteristics and allowing simple Shannon’s theorem-bascd design by using small cell library.
BASIC GDI FUNCTIONS:
GDI method is based on the use of a simple cell as shown in Fig 1. At a first glance the basic cell reminds the standard CMOS inverter, but there are some important differences: GDI cell contains 3 inputs – G (common gate input of nMOS and PMOS), P (input to the source/drain of PMOS) and N (input to the source/drain of nMOS).
Most of these functions are complex (6-12 transistors) in CMOS, as well as in standard PTL implementations, but very simple (only 2 transistors per function) in GDI design method. The reasons for this are as follows: (1) F1 is a complete logic family (allows realization of any possible 2-input logic function), (2) FI is the only GDI function that can be realized in a standard p-well CMOS process, because the bulk of any nMOS is constantly and equally biased.
As can be seen, GDI cell structure is different from the existing PTL techniques, and has some important features, which allows improvements in design complexity level, transistor count, static power dissipation and logic level swing . Understanding of GDI cell properties demands a deeper operational analysis of the basic cell in different cases and configurations.
- GDI technique has lesser delay, high density circuits and low power consumption.
- It uses low area.
- Simple hardware implementation.