Source : Verilog HDL

Proposed Abstract:

In image processing and computer vision, pixel shuffling is a method used to increase an image’s resolution without adding more parameters or network complexity. With this technique, a low-quality image’s pixels are rearranged to produce an output with a better resolution. Pixel shuffling has proven successful in a number of applications, such as image synthesis, super-resolution, and style transfer. Its simplicity and efficiency make it an attractive option for tasks where increasing image resolution is essential, while avoiding the computational overhead associated with more complex architectures. The image line buffer based pixel shuffling technique presented in this study is an alternative to the classic method, which takes up more logic space in VLSI implementations. This proposed method splits and reconstructs the source photos using a 5×5 image line buffer. With the use of block interleave techniques, this pixel shuffling approach handled row and column sequence using this 5×5 picture line buffer. In conclusion, this study was compared with the PSNR and SSIM value; comparisons of logic sizes for area, latency, and power were also examined.

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