FPGA Implementation of Reversible Logic based Vector Mode Systolic Array Multiplication

• To design the Martix Multiplication using Checksum based Error Detection at two different Modes using Array Multiplier, its configured with Conventional and Reversible logic Full Adders for area, delay and power reduction.

• Mode 1 : Bit Mode, this mode will designed using 4×4 Matrix Multiplication and Detect the Error using Checksum Method.

• Mode 2 : Vector Mode, this mode will designed using 4×4 Matrix Multiplication, in the Systolic array of processing element we have used Array Multiplier with Conventional and Reversible logic method to detect the Error using Checksum.

• Modelsim
• Xilinx

Proposed System:

In this research, a strategy for achieving energy savings via decreased voltage operation is suggested. By incorporating Algorithm Based Fault Tolerance (ABFT) into a digital architecture, the solution identifies timing issues. Using a systolic array matrix multiplier running at decreased voltages and identifying faults on the fly to prevent energy-intensive memory round-trips, this method has been developed. To design the prposed work of this paper presents a Martix Multiplication using Checksum based Error Detection at two different Modes using Array Multiplier, its configured with Conventional and Reversible logic Full Adders for area, delay and power reduction. Mode 1 : Bit Mode, this mode will designed using 4×4 Matrix Multiplication and Detect the Error using Checksum Method. Mode 2 : Vector Mode, this mode will designed using 4×4 Matrix Multiplication, in the Systolic array of processing element we have used Array Multiplier with Conventional and Reversible logic method to detect the Error using Checksum. This work was produced at Verilog HDL, synthesized on Xilinx Vertex-5 FPGA, and all of the characteristics were analyzed and compared in terms of area, latency, and power.

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Algorithm Level Error Detection in Low Voltage Systolic Array