Proposed Title :
CMOS Implementation of 45nm and 65nm Two Stage Operational Transconductance Amplifier with all Subthreshold MOSFETs
Improvement of this project :
To design Two Stage OTA at 65nm and 45nm CMOS Technology and compared all the parameters in terms of area, delay and power.
Input voltage given to 1.2V for 65nm, and 0.8V for 45nm, instead of1.6V for 0.5um CMOS Technology from the base paper.
- Tanner EDA
In this paper presents a operational trans-conductance amplifier (OTA) to provide a novelty for an ultralow voltage (ULV), ultralow power (ULP). An approach for the design of two-stage class AB OTAs with sub-1µA current consumption is proposed and demonstrated. The approach employs MOS transistors operating in subthreshold and allows maximum gain-bandwidth product (GBW) to be achieved for a given DC current budget, by setting optimum distribution of DC currents in the two amplifier stages. Thus, a straightforward class of AB low power efficient ULV structure have been acquire, which can work on the supply voltages below the threshold of the MOS transistors used. While simultaneously providing the common more range of the input rail to rail. The existing method of OTA based architecture was developed at 500nm CMOS technology using 1.6V. In the proposed method of Two Stage OTA architecture was developed at 45nm using 0.8V and 65nm using 1.2V CMOS technology, finally this work as developed in Tanner EDA tool, and proved the comparison of delay and power consumptions.
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Two-Stage OTA With All Subthreshold MOSFETs and Optimum GBW to DC-Current Ratio
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