Proposed Title :
FPGA Implementation of High Speed Approximate DADDA Multiplier using Parallel Prefix
adder with support of 4:2 Compressor
Improvement of this project :
To design the DADDA Multiplier using 4:2 Compressor, For final addition constructed using parallel prefix adder of Han Carlson and Kogge Stone adder.
We have designed 8×8 and 16×16 DADDA Multiplier for performance analysis.
A new sector of high-speed error-tolerant circuits combining approximation computing is emerging to meet the growing need for high-speed multimedia applications. As a result, certain applications deliver excellent performance at the tradeoff of decreased accuracy. Furthermore, such techniques simplify system design while minimizing latency and power consumption. This paper analyses and proposes the design and analysis of two approximation compressors with decreased space, delay, and power consumption while keeping comparable accuracy and performance when compared to existing systems. This work’s suggested architecture included a 4:2 compressor in 8-bit and 16-bit DADDA multipliers, and the final addition was constructed utilizing Han Carlson and Kogge Stone parallel prefix adders. When compared to state-of-the-art approximation multipliers, these multipliers exhibit more accuracy. The research is then expanded to forecast the suggested design’s use in error-tolerant applications such as picture smoothing and multiplication. Finally compared all the parameters in terms of area, delay and power.
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Approximate Multiplier Design Using Novel Dual-Stage 4 : 2 Compressors
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