Proposed Title :
FPGA Implementation of Two Speed Serial Parallel Booth Multiplier with Improving Robustness using Fault Detection Mechanism
Improvement of this project :
To increases the Robustness of Two Speed Radix -4 Serial and Parallel Booth Multiplier using Fault Detection Mechanism.
To develop the FDM Booth Multiplier at 8-bit, 16-bit, 32-bit and 64-bit, and compare all the parameters in terms of area, delay and power.
Integrated circuits are becoming increasingly susceptible to transient failure due to area reduction and external factors such as high-energy radiation, electrical noise and particle impact. As a results, the method for increasing the robustness of circuits against these errors have been around for a long time, but they either require a lot of additional logic sizes, changing the temporal behavior of the circuit. In this case study, we offer a new technique that overcomes these limitations by finding application specific circuit information, such as the relationship of the flip flops and when they assume the same value. As a same way proposed method of this work, applied this fault detection mechanism in serial and parallel arithmetic method of SQRT based Booth multiplier at 8-bit, 16-bit, 32-bit, 64-bit sizes to improve overall performance and reduce logic sizes with critical paths and increases the robustness of the multiplications, where compared to Wallace tree and DADDA multiplier. Finally this work will present in Verilog HDL and synthesized in Xlinx FPGA and proved all the comparisons in terms of area, delay and power.
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Determining Application-Specific Knowledge for Improving Robustness of Sequential Circuits
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