Proposed Title :
FPGA Implementation of High speed and High precision Overlap Free Finite Field Multiplier using Karatsuba Method
Improvement of this Project:
To re-modified the 2-bit DFG Hardware Implementation of Karatsuba Multiplier with 4-bit output method.
To develop the Overlap and Non-Overlap design of 4-bit, 8-bit, and 16-bit DFG Karatsuba Multiplier using Proposed Modified 2-bit DFG Karatsuba Multiplier and compared all the parameters to the existing 4-bit, 8-bit and 16-bit Karatsuba Multiplier.
Cryptography systems have become indispensible components of nearly every communication equipment. Among cryptographic techniques, public-key cryptography, particularly elliptic curve cryptography (ECC), has emerged as the dominant protocol at the moment. Polynomial multiplication is recognized as the slowest and most area-consuming process in ECC systems. This paper presents a unique hardware design for efficient FPGA implementation of Finite field multipliers for ECC. The proposed approach for modifying the high speed overlap free karatsuba multiplier at a 2-bit design flow graph of Hardware Implementation with a 4-bit output method. The present 2-bit design flow graph approach has only a 3-bit output method, which does not guarantee a valid output at high precision bits. This research also reported the Overlap and Non-Overlap design of 4-bit, 8-bit, and 16-bit DFG Karatsuba Multiplier employing Proposed Modified 2-bit DFG Karatsuba Multiplier and compares all parameters to the current 4-bit, 8-bit, and 16-bit Karatsuba Multiplier.
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An Efficient and High Speed Overlap Free Karatsuba Based Finite Field Multiplier for FPGA Implementation
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