Proposed Title :
A 16nm CMOS Implementation of 4×4 Array of SRAM utilizing Low Standby Power 10T SRAM Cell With Expanded Static Noise Margins
Improvement of this project :
To develop a single-bit SRAM of LP10TSRAM, as well as a 6T SRAM, using CMOS technology with a 16-nanometer process.
To build a 16 nm 4×4 array of SRAM utilizing LP10TSRAM while minimizing the amount of space, delay, and power used in the process.
- Tanner EDA
The purpose of this study is to investigate a low standby power 10T (LP10T) SRAM cell that has strong read stability and write-ability (RSNM/WSNM/WM). A robust cross-coupled structure is used by the proposed LP10T SRAM cell. This structure is comprised of a normal inverter with a stacked transistor as well as a Schmitt-trigger inverter with a double-length pull-up transistor. The read-disturbance is eradicated as a result of both this and the separation of the read path from the real internal storage nodes. In addition to this, it is able to carry out its write operation in pseudo differential form by using a write-assist mechanism, which makes use of the write bit line and control signal. Using Tanner EDA’s 16-nm CMOS, to predictive technology model at 0.5 V supply voltage, and temperature fluctuations are used to estimate the performance of the proposed LP10T SRAM cell by comparing it to various state-of-the-art SRAM cells. This comparison is done utilizing temperature variations. The suggested design was created at a 4×4 Memory array utilizing LP10T SRAM, with the goal of increasing the memory bit size as well as the storage capacity of the system. Tanner EDA Tool was used to design this work using 16nm CMOS technology. Area, power, and other parameters were compared with single bit SRAM Cells.
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A Reliable Low Standby Power 10T SRAM Cell With Expanded Static Noise Margins
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