Proposed Title :
FPGA Implementation of XOR-MUX Full adder based Approximate 4-2 Compressors for Low-Power Approximate Multipliers
Improvement of this Project:
In the proposed three type of accuracy based approximate 4:2 given in Fig.3 (a), (b), (c) as per the equation (5), (6), (7), (8) and (9). In this proposed 4:2 compressor will required a full adder to find out sum and carry operation.
Here, the compressor and full adder based architecture, these conventional full adder will take more logic size, thus proposed modification will reduce the number of logic gate in full adder which using XOR-MUX highly synchronization full adder.
In normal full adder circuit will have to design 5 logic circuit, but XOR-MUX full adder will used only 2 logic gate and 1 multiplexer, it will take minimum logic of area, delay and power compared to conventional full adder based 4:2 compressor.
This proposed work of 8×8 unsigned multiplier using XOR-MUX Full adder with 4:2 Compressor will have designed in Xilinx FPGA and proved the performance of area, delay and power.
In this paper, We proposed three different accurate 4:2 compressor with using high speed gate level full adder design of XOR and Multiplexer circuit instead of conventional full adder design. Which have the flexibility of switching between the exact and approximate computing operating modes. In this approximate mode, these dual quality compressor provide high speed and low power consumptions at the cost of lower accuracy. Each of the compressor has its own level of accuracy in the approximation mode as well as different delay and power dissipations in the approximate and exact modes. Using these compressors in the Approximate multiplier, it will provide accuracies as well as the power and speed may change dynamically during the runtime operations. The proposed 4:2 compressor based approximate multiplier save few number of logic gates in partial product, and this proposed multiplier was evaluated in image processing application, such as image multiplication, image sharpening, and so on. This design was implemented in Verilog HDL, and synthesized in Xilinx S6LX9 FPGA and compared all parameters in terms of area, delay and power.
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Comparison and Extension of Approximate 4-2 Compressors for Low-Power Approximate Multipliers
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