Proposed Title :
FPGA Implementation of Area, Delay and Energy Efficient XOR-MUX Full Adder Based Binary Tree Multi-Operand Adder
Improvement of this Project:
To reduced number of logic gates in multi operand binary tree adder, here the proposed work used XOR-MUX based full adder instead of AOI & OAI method.
The AOI method will work same as conventional full adder method, it’s not reduced any number of logic gates in multi operand binary tree adder.
The OAI method will functioning with inverter of AOI method, in this case it will take more number of inverter logic in multi operand binary tree adder.
The proposed method of this work introduced a XOR-MUX level synchronization method in multi operand binary tree adder for that 3 number of logic gates reduced in each full adder and finally proved the performance of area, delay and power.
- Modelsim 6.5b
- Xilinx 14.5
The essential path of the binary tree adder (BTA) based ripple carry adder (RCA) is studied here to find the possibilities of minimization of delay. The new logic formulation and the subsequent configuration of RCA was proposed for the BTA based on the results of the study. The effect, of the comparison indicates that the proposed RCA architecture provides better performance than the current RCA in terms of area, delay and energy consumptions. Similarly, in the BTA architecture of AOI, OAI method will also take more area and power consumptions. Therefore, in this proposed work will introduced, XOR-MUX full adder in BTA architecture and reduced the area, delay and power compared to AOI and OAI based BTA architecture. Finally this work presents in Verilog HDL, and synthesized this work in Xilinx FPGA, and proved the performance of area, delay and power.
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Area Delay and Energy Efficient Multi-Operand Binary Tree Adder
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