Proposed Title :
FPGA Implementation of 4:2 Compressor based Wallace Tree Multiplier using Parallel Prefix Adder for High Speed Applications
Improvement of this Project:
To improve the Wallace tree multiplier using 4:2 compressor method and reduced number of stages
To design three different parallel prefix adder and integrated in final addition of Wallace tree multiplier and prove the performance of area, delay and power.
In any digital gadgets application based arithmetic operations a multiplier will take major role to support several multiplication algorithms, by the way it’s taken more logic size and power consumptions. As per the research of last few decades among various multiplication algorithm, a Wallace tree multiplication will provide effective terms of low logic sizes and more speed of operations. In a recent arithmetic applications based circuit design will have more demand with high speed and low area, in this manner the proposed approach of this work will improve the speed of Wallace tree multiplier using 4:2 compressor method without degrading its area parameter. Thus, the proposed method will integrate more efficient and more reliable Kogge stone parallel prefix, Brent kung parallel prefix, Sklansky parallel prefix, Ladner Fischer parallel prefix, Han Carlson parallel prefix addition operation in the Wallace tree multiplication on final addition stage at 16-bit data width. Similarly the proposed multiplication will designed using Verilog HDL, and Synthesis in Xilinx Spartan-6 FPGA, and hence proved all the parameters in terms of number of LUT, slice registers, IOB, delay and power.
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Design and analysis of High speed Wallace tree multiplier using parallel prefix adders for VLSI circuit designs
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