Proposed Title :
A 22nm and 16nm CMOS Implementation of Low Power and High Speed Hybrid Logic Full Adder using High Performance 10-T XOR-XNOR Cell
Improvement of this Project:
To re-modified the full adder design of 4 different circuits, and correct the errors.
To design this 4 different full adder logic circuits at 22 nm and 16 nm CMOS Technology and compared all the parameters.
- Tanner EDA
In a recent arithmetic technology, a hybrid logic style is commonly used to introduce complete full adder circuits. The efficiency of the XOR-XNOR circuit determines the performance of the hybrid full adder in terms of delay, power and driving capability. In this paper presents a high speed low power 10-T XOR-XNOR circuit with full swing outputs and enhanced delay efficiency. The proposed method where simulated in Tanner tool using 22nm and 16nm CMOS technology. This proposed method also designed four different full adder design that makes use of the proposed XOR-XNOR circuit and usable sum and carry modules. In the terms of power delay product. The proposed full adder was embedded in 8-Bit cascaded full adder architecture to test their driving capabilities.
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High-Speed Hybrid-Logic Full Adder Using High-Performance 10-T XOR–XNOR Cell
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