Proposed Title :
FPGA Implementation of Low Complexity Iterative Methods of Column and Row Wise Matrix Vector Multiplication
Improvement of this project :
To design Row Wise Matrix Vector Multiplication and Column Wise Matrix Vector Multiplication using LSTM Vector Method.
The Row Wise Matrix Vector implemented with Row Bypass Multiplier
The Column wise Matrix Vector implemented with Column Bypass Multiplier
This Row and Column Vector Multiplication design with Sliding Function at 8×8 Matrix Size.
This article describes a fine-grained column-wise matrix–vector multiplication accelerator that may be reconfigured for use with recurrent neural networks. We propose a new latency-hiding architecture for recurrent neural network acceleration that uses column-wise matrix–vector multiplication rather than the state-of-the-art row-wise operation. This will allow us to reduce the amount of time needed for acceleration. The throughput of recurrent neural network inference systems may be significantly improved by eliminating data dependencies using this hardware architecture’s capabilities. In addition, we provide a checkerboard tiling method that is both adjustable and incorporates a variety of combinations of element-based and vector-based parallelism. This allows for the use of huge weight matrices without compromising the efficiency of the computation. The LSTM Vector Method was used to construct the suggested work of this design, which consisted of developing Row Wise Matrix Vector Multiplication and Column Wise Matrix Vector Multiplication. Row Bypass Multiplier is used in the implementation of the Row Wise Matrix Vector. The implementation of the Column wise Matrix Vector using the Column Bypass Multiplier. This design utilizes both row and column vector multiplication and has a sliding function. In the end, this work was produced in Verilog HDL, synthesized on Xilnx Vertex-5 FPGA xc5vlx330-2ff1760, and all of the parameters were compared with regard to area, delay, and power.
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Recurrent Neural Networks With Column-Wise Matrix–Vector Multiplication on FPGAs
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