Proposed Title :

High Speed and Approximate Wallace
Optimized Ternary Multiplier Design for FPGA Applications

Improvement of this project :

• This work was proposed, Ternary Unbalance arithmetic Wallace Tree multiplier design, was developed in Front-End VLSI, for more number of Front-End applications.

• FPGA based Novelty architecture will be created for CGEN, CSEL (Unbalanced) based from the LUT.

• Novelty of Proposed final addition update with Ternary Excess Converter to reduce the number of logic in Final Addition.

Software Implementation:

• Modelsim
• Xilinx

Proposed System:

It is challenging to employ existing ternary multiplier designs in ternary systems. Thus, ternary Wallace tree multipliers are presented to enhance the functionality of current ternary multipliers by using 4-input ternary adders to decrease the number of logic sizes and power consumptions. As a carry-chain adder for the Wallace tree multiplier, a ternary carry-select adder is also proposed to shorten the carry propagation latency. It is proposed that a ternary full adder with a comparable cell delay be replaced with a 4-input ternary adder to calculate one more input. To decrease the quantity of partial products produced by the 4-input ternary adder, a ternary Wallace tree structure has been proposed. In addition, a fast carry chain adder called a ternary carry-select adder is recommended to reduce the latency of the ternary Wallace tree’s final step. The carry-generate (CGEN) and carry-select (CSEL) ternary logic gate types are suggested for the adder’s design. For further Front-End FPGA applications, a Ternary Unbalance arithmetic Wallace Tree multiplier architecture was created in Front-End VLSI. Novelty of Proposed final addition update with Ternary Excess Converter to reduce the number of logic in Final Addition. To improve the speed of operations, a novel design based on FPGA will be developed for CGEN, CSEL (Unbalanced) based on LUTs will be employed. This project used Xilinx Vertex-5 FPGA to synthesize the Verilog HDL design, and it compared all of the parameters’ area, delay, and power values.

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Optimizing Ternary Multiplier Design with Fast Ternary Adder