Proposed Title :
FPGA Implementation of Majority Logic using Lower Part Approximation Adder for Probability Driven Evaluation
Improvement of this project :
To design a Existing LOA and LXOA Design and Compared the Error Rate with Accurate Ripple Carry Adder.
To design a Novelty based Majority Gate using Half Adder and Majority Gate using Full adder and Majority Half Adder using Excess one converter.
To design a LXOA Approximate Adder design using Novelty based Majority Gate Full Adder and Half Adder and Excess one converter.
The Proposed work, reduced the number of errors in addition output to the existing LOA, LXOA Approximate Adder.
Carry chains may sometimes represent critical pathways in parallel prefix adder topologies, which can restrict speed and, as a result, efficiency. We examine several approximation strategies that reduce the length of the carry chain by offloading the lower-part of the computation to a more approximate unit. Using probability theory, we are able to develop models of their correctness. In addition, the work that will be presented in this article will provide a Novelty-based Majority Gate that uses a Half Adder, as well as a Majority Gate that uses a Full Adder, and a Majority Half Adder that uses an Excess one converter. In addition, to create an LXOA Approximate Adder employing Novelty-based Majority Gate Full Adder and Half Adder and Excess one converter, with the goal of reducing the number of errors in addition output to the current LOA, LXOA Approximate Adder. In the end, this work was produced using Verilog HDL, and each parameter was evaluated based on its impact on area, latency, and power consumption.
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Probability-Driven Evaluation of Lower-Part Approximation Adders
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