Proposed Title :
Booth Multiplier-based and WALLACE Tree Adder-based Tiny Yolo CNN Implementation in FPGA with Reduced Hardware Resources Based on XOR-MUX Full Adder
Improvement of this project :
- To design adder tree structures of modified booth encoding multiplier and Wallace tree multiplier design with XOR-MUX full adder design, and compared to Conventional full adder design.
The Convolutional Neural Network, often known as CNN, has achieved a high level of accuracy and is being used extensively in the image identification process. Recent years have seen a proliferation of current applications that are powered by deep learning, which presents a formidable obstacle for the research and development of hardware implementation. As a result, hardware optimization for the effective accelerator design of CNN continues to be a difficult problem. A processing element (PE) that is responsible for carrying out the convolution operation is an essential part of the architecture of the accelerator. This article presents a novel processing element design as an alternative method for the implementation of hardware. The goal of this design is to lower the quantity of hardware resources and the amount of power used. It has been suggested that a modified BOOTH encoding (MBE) multiplier and WALLACE tree-based adders may respectively take the place of bulky MAC units and the usual adder tree. Similarly, the multiplier architecture will occupy number of conventional full adder, it will take more logic size compare to XOR MUX full adder design, here we have present this work with XOR-MUX full adder instead of Conventional full adder design. Finally, this work was developed using Verilog HDL, and synthesize in Xilinx Vertex-5 FPGA, and compared all the parameters in terms of area, delay and power.
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Power Efficient Tiny Yolo CNN Using Reduced Hardware Resources Based on Booth Multiplier and WALLACE Tree Adders
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