Proposed Title :
FPGA Implementation of Dual Clock 4-Slot Mesochronous FIFO Buffer using 128 Data Width
Improvement of this Project:
Increases the data width up to 128 bits, and prove the performance with existing data width 64 bits.
Designed 4-Slot deep structure at 128 data width.
- Xilinx 14.2
Completely synchronous clocking is replaced by more relaxed clocking systems, such as mesochronous clocking, to improve device composability and promote timing elimination. In this framework, the modules receive the same clock signal at both ends of the mesochronous interface, while working under the same clock frequency, but the edges of the arriving clock signals can have an undefined phase relationship. In such instances, when transmitting data through modules, clock synchronisation is required. In this paper, we introduce a new mesochronous first-input-first-output (FIFO) dual-clock buffer that can accommodate both clock synchronisation and temporary data storage by implicitly synchronising data while specifically synchronising only the flow-control signals. And when the transmitter and the receiver are separated by a long connexion whose delay cannot match into the target operating frequency, the proposed design can work correctly. The suggested mesochronous FIFO can be expanded in such situations to support multicycle connexion delays in a modular way and with limited adjustments to the baseline architecture. The new architecture is seen to deliver a significantly lower cost implementation as compared to the other state-of-the-art dual-clock mesochronous FIFO designs. Finally this work developed at 128 and 64 data width and proved the performance of area, delay and power consumptions.
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The Mesochronous Dual-Clock FIFO Buffer
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