Proposed Title :
FPGA Implementation of Highly Secure Forward Error Correction Method of Rand Shift based 128-bit Advance Encryption Standard (AES)
Improvement of this Project:
To design a Rand Barrel Shift Method using 128 AES Encryption and Decryption technique in single architecture. To configure Cache and Memory Block size at 32-bit word, also differentiate the architecture and removed the number of multiplexers.
- Xilinx 14.2
In this study, we present to reduce a stuck at faults in safe resistive primary memory architecture, it will reduce more energy and area efficient compare to the previous stuck at fault method. In this proposed process, a large number of memory position with stuck at faults may be used to correctly store the data by using the random features of the encrypted data by using Advance Encryption Standard (AES) as well as rotational shift operations. In energy consumptions is significantly reduce than that of other recently introduced approaches due to specific hardware implementation of the proposed system. Along with other error correction technique, including the error correction code (ECC) and error correction pointer (ECP), this technique can be used. It is applied in a phase change memory (PCM) based main memory device, and compared to three error tolerance approaches in order to determine the effectiveness of the proposed process. More broadly, we illustrate, that the fault coverage of the proposed system is close to that of the state of the art method. In this step, a Rand Barrel Shift method can be build using 128 AES Encryption and Decryption in a single architecture with configure the size of the cache and memory block size. This work was designed in Verilog HDL and synthesized in Xilinx VERTEX FPGA, and finally compared all the parameters in terms of area, delay and power.
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RandShift: An Energy-Efficient Fault Tolerant Method in Secure Nonvolatile Main Memory
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