Low-Power High Precision Floating-Point Divider With Bidimensional Linear Approximation
Low-Power High Precision Floating-Point Divider With Bidimensional Linear Approximation
Abstract:
In this paper we propose a novel approximate floating-point divider based on bidimensional linear approximation. In our approach, the mantissa quotient is seen as a function of the two input mantissas of the divider. The domain of this two-variable function is partitioned into n×n subregions, named tiles, where n×n are chosen as powers of two. In each tile the quotient is approximated with a linear combination of the input mantissas. To achieve fine accuracy, an optimization problem is formulated within each tile to determine the optimal coefficients for the linear combination, which minimize the Mean Relative Error Distance (MRED) of the divider. Furthermore, to make hardware implementation more effective, the minimization problem is appropriately modified to search for simplified coefficients. The hardware structure of the divider only requires a small look-up table to store the linear approximation coefficients, and can carry saved operations. The proposed architecture is highly efficient and accurate over a wide range of accuracy, depending on the number of tiles chosen for the approximation. The obtained results demonstrate error performance and hardware features superior to the state-of-the-art. The proposed dividers define the Pareto front in area–delay–product vs. MRED, for MRED down to 1.2×10⁻². Application results for JPEG compression and tone mapping further highlight the strength of the proposed divider, which exhibits Structural Similarity Index (SSIM) over 0.99 in all cases and Peak Signal-to-Noise Ratio (PSNR) up to 45 dB.
Index Terms:
Floating-point divider, approximate computing, linear approximation, error distance.
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Low-Power High Precision Floating-Point Divider With Bidimensional Linear Approximation
