A Comparative Analysis of Low Temperature and Room Temperature Circuit Operation
A Comparative Analysis of Low Temperature and Room Temperature Circuit Operation
Abstract:
Low-temperature (LT) conditions can potentially lead to lower power consumption and enhanced performance in circuit operations by reducing the transistor leakage current, increasing carrier mobility, reducing wear-out, and reducing interconnect resistance. We develop PROCEED-LT, a pathfinding framework to co-optimize devices and circuits over a wide performance range. Our results demonstrate that circuit operations at LT (−196 °C) reduce power compared to room temperature (RT, 85 °C) by 15× to over 23.8× depending on performance level. Alternatively, LT improves performance by 2.4× (high-power, high-performance) – 7.0× (low-power, low-performance) at the same power point. These gains are further improved in low-activity circuits and when using bimodal configurations. Meanwhile, we highlight the need for improvement in Vth variation to leverage benefits at cryogenic temperatures.
Index Terms —
77 K, circuit optimization, cryogenic computing, FinFET, Pareto optimization, process variations, transistor aging.
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