A Pay-Per-ISE RISC-V Processor With Hardware-Assisted Orthogonal Obfuscation
A Pay-Per-ISE RISC-V Processor With Hardware-Assisted Orthogonal Obfuscation
Abstract:
Security and cost efficiency are of utmost importance for embedded processors when it comes to limiting hardware resources in IoT applications. This brief presents a security reduced instruction set computer-five (RISC-V) specific instruction set extension (ISE) designed based on hardware-assisted orthogonal obfuscation for hardware security. The orthogonal obfuscation defines an architecture geared toward high-security processors that supports a Pay-Per-ISE function using a key management unit (KMU), thus capable of securing the function and usage of the key for a user’s partially authorized ISE and controlling the unlocking of the specific ISE. The proposed security RISC-V test chip is fabricated in a 65-nm CMOS technology with a core area of about 0.739 mm². The measured results demonstrate that our processor realizes the instruction set authorization function. The results show an average power of 5.28 mW at 1.2 V, a hardware overhead of <3% at 50 MHz, and a 30% improvement in security.
Index Terms —
Instruction set authorization, orthogonal obfuscation, Pay-per-instruction set extension (ISE), reduced instruction set computer-five (RISC-V).
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