AdAM: Adaptive Approximate Multiplier for Fault Tolerance in DNN Accelerators

Objective:

• To design a leading one detector with leading output and also log value.
• To remodified the Barrel left shifter with truncated variable method using leading detection. Here, the bit will be shifted left with number of zeros as per leading input.
• Instead of traditional adaptive adder using RCA & CLA, we introduced a Hybrid adaptive PPA adder with Brent kung and kogge stone adder.
• The truncated bits (t) and higher-order bits (h) are treated as variable parameters rather than fixed constants.
• The design of Hybrid adaptive addition done with two PPA adder, for LSB addition using with Brent Kung adder and the MSB addition using with Kogge stone adder. Here, this adder designed with 8-bit and 16-bit architecture.
• For log value addition in the top module architecture, this proposed work design with Brent kung adder.
• Finally, Antilogarithm function will decide the output with support of log(n)+1. It will have shifted the value from Adaptive Hybrid sum value, as per logarithmic function of X = 2^(log_ab) × Mantissa.
• Finally, we developed this work in Verilog HDL, and verified functionality in Modelsim, and synthesize using Xilinx Vertex-5 FPGA, and compared all the parameters in terms of LUT, Slice registers, delay and power.