Proposed abstract:
Approximate and reversible computing are increasingly used in low-power signal processing, medical imaging, and machine learning applications, where small inaccuracies can be accepted to achieve reductions in power, area, and delay. These methods offer more advantages such as lower switching activity and reduced heat dissipation in approximate method, but they also face limitations including error accumulation and the need for efficient alternative structure, thus this work design using reversible gate structures to keep logic cost minimal. Existing reversible approximate full adders have lot of design, but it will present with more error analysis. This projects aims to design a error reduction in reversible approximate full adder with lower cost and controlled error behavior. For, that this work, present with a new approximate full adder which using only one PERES gate and one Feynman gate is introduced to reduce the number of reversible gates, constant inputs, and garbage outputs while confining approximation to the least-probable input combination to avoid major error propagation. Existing examples of RAFA-1 and RAFA-2 based reversible adder designs are used for comparison to highlight the improvements in logic size and error rate. Additionally, this design also developed a proposed adder to build reversible 4:2, 5:2, and 7:2 compressors and an approximate multiplier architecture, allowing evaluation of how the new full adder behaves inside higher-order arithmetic blocks. The entire design is described in Verilog HDL, functionally verified using ModelSim, and synthesized on a Xilinx FPGA to measure LUT usage, slice registers, delay, and overall hardware efficiency.
Software Implementation:
- Modelsim & Xilinx
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Design and analysis of Reversible Approximate Full Adder and its applications with Optimized 4:2, 5:2, 7:2 Compressors for Efficient Approximate Multipliers
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