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A Lower Power Reduced Error Lower Part OR Adder for Multimedia Applications
Original price was: ₹10,000.00.₹6,000.00Current price is: ₹6,000.00.
Source : Verilog HDL
Base paper abstract:
With the use of multimedia applications, machine learning, and signal processing, approximate computing has become increasingly popular in the pursuit of power-efficient and high-performance architectures for mobile devices. The arithmetic unit is the key component that determines the performance of the overall design. Therefore, in this paper, a novel low-power reduced error lower part-OR adder (RELOA) is proposed. In the proposed architectures, the input bits are divided into three parts, and the sum is computed accurately or approximately based on their significance in the overall sum. The sum of the most significant bits is calculated accurately to have better design metrics, while the least significant bits are approximately to reduce implementation complexity. The proposed architecture offers 16% less power and 9.37% reduction in error metric over existing adders while maintaining a similar delay. Additionally, when processing digital images, the proposed architecture displays good image quality comparable to existing approximate adders.
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1. Source code ( Modelsim/ Xilinx/ Quartus/ DSCH3/ Microwind)
2. Existing and Proposed Project Comparison with output video
3. Basic Documentation (20 to 30 Pages):
3.1 Proposed Title
3.2 Proposed Abstract
3.3 Advantages & Disadvantages
3.4 Improvement of this Project
3.5 Existing System with Notes
3.6 Proposed System with Notes
3.7 Literature Survey
3.8 Software Related Notes
3.9 VLSI and HDL Language / Tanner Notes
3.10 References & Reference Paper for More Pages
4. Online Support ( Any Desk / Zoom / Google Meet)
Proposed abstract:
Approximate adders are widely used in multimedia processing, image filtering, machine learning accelerators, and low-power DSP systems where small computational errors can be tolerated in exchange for improved energy efficiency and reduced hardware cost. These designs offer advantages such as lower area, reduced power consumption, and simplified logic implementation; however, aggressive approximation can introduce significant error, bias in computation, and degradation in output quality as operand size increases. The Reduced Error Lower Part OR Adder (RELOA) is one such architecture that applies 50% approximation to reduce hardware complexity, but this high level of approximation leads to increased mean error distance and mean square error, especially for larger word-length operations. Existing designs primarily focus on power reduction while compromising accuracy, and limited work has addressed scalability with improved precision. To overcome this issue, this work proposes a modified RELOA architecture that reduces approximation to 25% by removing the constant logic block and confining controlled approximation only to the least significant quarter of the operand while maintaining carry-aware logic. This structural modification significantly improves computational accuracy while preserving most of the hardware benefits of approximate computing. The proposed architecture is designed for 16-bit, 24-bit, and 32-bit word lengths using structural Verilog HDL and synthesised on a Xilinx Virtex-5 FPGA. Performance is evaluated in terms of LUT utilisation, registers, delay, and power, along with error metrics such as MED and MSE. The results demonstrate improved accuracy with moderate hardware overhead, and scalability analysis shows that delay variation reduces at higher word lengths, making the proposed design suitable for precision-aware multimedia and DSP applications.
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Scalable Accuracy Enhanced RELOA Architecture with 25% Controlled Approximate for Low Power DSP Applications
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