In this article, an efficient architecture for a low-power, high-resolution flash analog-to-digital converter (flash ADC) is presented. It operates at 12-bit resolution with a sampling frequency of 1.1 GS/s. The architecture is a segmented one consisting of three subflash ADCs that we call SADC1, SADC2, and SADC3. During the operation, SADC1 detects the MSB bit, and SADC2 detects the intermediate bits, while SADC3 detects the finer bits of the flash ADC. Furthermore, SADC1 has a 1-bit resolution, SADC2 has a 6-bit resolution, and SADC3 has a 5-bit resolution. The binary operation related to 12-bit resolution is achieved by combining the subflash ADCs, thermometer digital outputs, and an encoder. The ADC has been fabricated in Global Foundry (GF) 65-nm standard CMOS process. The measured performance parameters show a differential nonlinearity (DNL) of ±0.24 LSB, an integral nonlinearity (INL) of ±0.45 LSB, a signal-to-noise and distortion ratio (SNDR) of 64.55 dB, a spurious-free dynamic range (SFDR) of 73.9 dB, and an effective number of bits (ENOB) of 10.43 bits. Also, power consumption is found to be 15.10 mW at 1.1-GS/s sampling frequency and 1.2-V supply voltage. The ADC achieves an FOM of 9.95 fJ/conversion-step (c-s) at the Nyquist input frequency and occupies a core area of 0.084 mm2.
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