A receiver for a three-lane 6-Gb/s/lane serial link has been developed in 28-nm CMOS technology. It incorporates an intrapair skew compensator (IPSC) and a three-tap decision feedback equalizer (DFE). The IPSC removes the IPS in analog front end by adding differential and common-mode signals of a differential pair. The three-tap DFE is realized with clock and data recovery (CDR) circuit with minimum hardware complexity. The receiver consumes 31.0 mW/lane at 6 Gb/s/lane and occupies an active area of 0.08 mm 2 .
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A 6-Gb/s Wireline Receiver With Intrapair Skew Compensation and Three-Tap Decision-Feedback Equalizer in 28-nm CMOS