This brief presents a memory-reduced hardware architecture for acquiring the frequency of sinusoidal signal based on the interpolated discrete Fourier transform (IpDFT). By exploiting the sparsity of the sinusoidal signal in the frequency domain, a spectrum compression method that can remove the unnecessary spectral lines is proposed together with the corresponding parameter extraction scheme, which circumvents the large-point DFT computation involved in the conventional IpDFT and thereby reduces the memory consumption markedly. On this basis, a low-latency hardware architecture is designed for the proposed frequency estimator. Implementation results demonstrates the proposed work can gain satisfactory accuracy while retaining low hardware cost and latency.
Software Implementation:
Modelsim
Xilinx
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A Memory-Reduced Frequency Estimator for the Measurement of Sinusoidal Signal
