This paper presents a novel spread-spectrum clock (SSC) tracking aid for digitally-controlled clock and data recovery (CDR) loops. The proposed tracking aid accurately recovers the time instants when the slope of the incoming data frequency ramp changes its polarity, so that the CDR can preemptively compensate the timing errors that can otherwise be incurred when relying on feedback controls only. Compared with the existing SSC tracking aids, the proposed tracking aid’s integration-based mean-tracking loop, comprising an integrator and subsequent negative feedback loop, achieves the superior noise resilience and SSC timing accuracy. The analysis shows that the error in recovering the SSC deflection timing can be as low as 0.01% of the SSC modulation period in case of tracking a triangular SSC profile and the error does not exceed 1.5% even when the SSC profile noise is increased to the signal-to-noise-plus distortion ratio of 20 dB. The behavioral simulation of a digitally controlled phase-locked loop (PLL)-based CDR employing the proposed SSC tracking aid demonstrates a 0.711-UI timing margin with a BER of 10-12, which is a 1.57× improvement in comparison with a PLL-based second-order CDR, when tracking a 6-Gb/s data stream modulated with a 30-kHz, 50 000-ppm extended triangular-shaped SSC profile.