This article presents the theoretical analyses and experimental results about jitter tolerance for delay-locked loop (DLL)-based clock and data recovery (CDR), which is generally used in an embedded clock serial link. From the proposed S-domain model, we prove that DLL-based CDR has superior low-frequency jitter tolerance than PLL-based CDR, whereas, assuming the ideal case, high-frequency jitter tolerance of DLL-based CDR is only a half of that of PLL-based CDR. In addition, the jitter tolerance characteristics of both PLL- and DLL-based CDRs are analyzed in a practical environment. Finally, the consistency of analysis is verified from measurement results using 2.7-Gb/s enhanced reduced-voltage differential signaling (eRVDS) receiver.
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An Analytical Jitter Tolerance Model for DLL-Based Clock and Data Recovery Circuits
