A soft-core analog-to-digital converter (ADC) based on multi-chain merged time-to-digital converter (TDC) is proposed. In hardware design, it only requires one resistor and an FPGA. The soft-core ADC is implemented in the FPGA. The FPGA-based ADC (FPGA-ADC) need to be calibrated including TDC length calibration, TDC alignment calibration and TDC-toADC code calibration. We implement the FPGA-ADCs with 1-, 2-, 4-, 6-, 8-chain merged TDC. The resulting FPGA-ADC can achieve a best resolution of more than 10 bits and a best 6.7 bits effective number of bits (ENOB) over a 0.67 to 2.03 V input dynamic range at a 200 MS/s sampling rate. The advantages of the proposed soft-core ADC are its compact size, reconfigurability and high resolution, which provides a feasible approach to achieve different readout electronics system on single hardware platform.
” Thanks for Visit this project Pages – Register This Project and Buy soon with Novelty “
